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71. 发明专利

JPH09261675A DEFLECTION YOKE, COLOR CATHODE RAY TUBE DEVICE USING THE DEFLECTION YOKE AND DISPLAY DEVICE 失效
公开(公告)号：JPH09261675A
公开(公告)日：1997-10-03
申请号：JP6504896
申请日：1996-03-22
申请人： HITACHI LTD , HITACHI MEDIA ELECTRON KK
发明人： OKUYAMA NORITAKA , FUKUMA KOJI , SAKURAI SOICHI , YOSHIOKA HIROSHI , TAKEYAMA ATSUSHI
IPC分类号： H04N9/28 , H01J29/76 , H01J31/20
摘要： PROBLEM TO BE SOLVED: To correct mis-convergence in longitudinal lines whose directions are opposite to each other in the middle of a screen and at upper and lower parts of the screen. SOLUTION: A series circuit consisting of an upper side auxiliary vertical deflection coil 7a and a resistor 14a, and a series circuit consisting of a lower side auxiliary vertical deflection coil 7b and a resistor 14b are connected in parallel, and a shunt circuit provided with diodes 18a-18d with different forward conduction voltage and polarity is connected in parallel with the resistors 14a, 14b, and the diodes 18a-18d are interconnected via a variable resistor 15a.

72. 发明专利

JPH09102592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09102592A
公开(公告)日：1997-04-15
申请号：JP8991196
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the memory capacity or large scale integration by providing a step buffer area made of a dummy conductor layer between a memory array and a peripheral circuit by sing a plurality of dynamic memory cells having a laminated capacitor as a memory cell formed in the memory array. SOLUTION: A memory chip has memory arrays M divided into four by cross areas made of areas A to E. The arrays M divided into the four are disposed by extending a word line in the lateral direction, and disposed by extending a data line (bit line or digit line) in a vertical direction. A step buffer area made of a dummy wiring layer is provided between the arrays M and the peripheral circuit. A guard ring is disposed under the step buffer area to stabilize the characteristics.

73. 发明专利

JPH0982224A CORRECTING LENS MEASURING EQUIPMENT FOR EXPOSURE DEVICE 失效
公开(公告)号：JPH0982224A
公开(公告)日：1997-03-28
申请号：JP22989495
申请日：1995-09-07
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI ELECTRON DEVICES KK
发明人： SEKINO YOSHIHIKO , MIYAKOSHI YOSHIZUMI , OHASHI ATSUSHI , MATSUDA HIROMI , YOSHIOKA HIROSHI
IPC分类号： H01J9/227
摘要： PROBLEM TO BE SOLVED: To measure the small surface angle of a correcting lens in a non- contact manner. SOLUTION: Laser beam is projected from a laser oscillator 15 to a correcting lens 7 and its transmitted light is received by a laser auto-collimator 16. The light receiving point of the laser auto-collimator 16 is picture-processed by a picture processor 30 to calculate a transmitted light refractive angle γ, so that the transmitted light refractive angle γ can be processed by a main control processor 34 to calculate the minute surface angle θ of the correcting lens 7.

74. 发明专利

JPH0946719A DEFLECTION YOKE, AND COLOR CATHODE-RAY TUBE DEVICE AND DISPLAY DEVICE USING SAME 失效
公开(公告)号：JPH0946719A
公开(公告)日：1997-02-14
申请号：JP19006595
申请日：1995-07-26
申请人： HITACHI LTD , HITACHI MEDIA ELECTRON KK
发明人： FUKUYAMA KOJI , OKUYAMA NORITAKA , SAKURAI SOICHI , YOSHIOKA HIROSHI , TAKEYAMA ATSUSHI
IPC分类号： H04N9/28 , H01J29/76
摘要： PROBLEM TO BE SOLVED: To correct the complicated erroneous convergence of a vertical line by changing a current made to flow to first and second auxiliary coils for vertical deflection corresponding to the direction and size of a vertical deflection current. SOLUTION: The first and second auxiliary coils 7a and 7b for the vertical deflection provided on the electron gun side of this deflection yoke and serially connected to a vertical deflection coil 3 are provided and the two kinds of diode circuits 18a and 18b of different forward direction conductive timings are anti-parallelly respectively connected to a first resistor 14a serially connected to the first auxiliary coil 7a and a second resistor 14b serially connected to the second auxiliary coil 7b. Then, the first and second resistors 14a and 14b are bypassed and the current made to flow to the first and second auxiliary coils is changed corresponding to the direction and size of the vertical deflection current. Thus, the correction direction of the erroneous convergence of the vertical line by the first and second auxiliary coils 7a and 7b is inversed and the erroneous convergence is made correctable.

75. 发明专利

JPH08115685A CATHODE-RAY TUBE DISPLAY DEVICE 失效
公开(公告)号：JPH08115685A
公开(公告)日：1996-05-07
申请号：JP25320894
申请日：1994-10-19
申请人： HITACHI LTD
发明人： JITSUKATA HIROSHI , KAWAKAMI KATSUYUKI , SAKURAI SOICHI , YOSHIOKA HIROSHI , SATO YOSHIO
IPC分类号： H01J29/88 , H01J29/76 , H01J29/98
摘要： PURPOSE: To effectively suppress two kinds of alternating electric fields radiated from the front by providing a canceling electrode in contact with the exterior wall of the glass container of a funnel portion, and forming a transparent conductive film on the outer surface of a faceplate. CONSTITUTION: An AC voltage produced in an internal conductive film on a cathode-ray tube 1 by electrostatic coupling as a result of a pulse voltage supplied to a deflection yoke 6, and a reverse pulse voltage applied to a canceling electrode 8 are made to cancel out each other, so that the amplitude of the AC voltage produced in the internal conductive film is reduced; i.e., of two kinds of alternating electric fields, VLEF, ELEF radiated to the front from the faceplate 3 of a tube 1, the VLEF is suppressed by supplying a reverse pulse voltage to the electrode 8 provided in contact with the glass container exterior wall of funnel portion 2 of the tube 1 where a cover graphite film 5 does not exist, so that the voltages cancel out each other; the ELEF is suppressed by setting to an optimum value the resistance value of a transparent coductive film formed on the surface of the plate 3 of the tube 1. Therefore, the two kinds of alternating electric fields can be suppressed to a specified value or below at reduced cost.

76. 发明专利

JPH07142008A IMAGE DISPLAY DEVICE 失效
公开(公告)号：JPH07142008A
公开(公告)日：1995-06-02
申请号：JP28473693
申请日：1993-11-15
申请人： HITACHI LTD
发明人： JITSUKATA HIROSHI , SAKURAI SOICHI , OKUYAMA NORITAKA , KAWAKAMI KATSUYUKI , YOSHIOKA HIROSHI
IPC分类号： H01J29/87 , H01J29/76 , H01J29/88 , H01J29/96 , H04N3/18 , H04N5/64
摘要： PURPOSE:To effectively restrain unnecessary radiation electric field emitted from the display surface of an image display device in which a cathode-ray tube is used. CONSTITUTION:A cancel electrode 8 formed outside of the funnel 2 of a cathode- ray tube device 1 is arranged between an armor graphite 5 to be earthed and the aperture of a deflection yoke 6 and a pulse voltage of polarity reversed to that of a pulse voltage applied to the deflection yoke is applied to the cancel electrode 8 from a high pressure deflection circuit 20. Thereby, unnecessary radiation electric field can be restrained by inducing, alternating electric field caused by the pulse voltage applied to the deflection yoke and alternating electric field caused by the reversed pulse voltage applied to the cancel electrode, inside the cathode-ray tube and canceling each other.

77. 发明专利

JPH0668667A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0668667A
公开(公告)日：1994-03-11
申请号：JP24275192
申请日：1992-08-19
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HOKKAI SEMICONDUCTOR
发明人： TSUNOSAKI MANABU , ISHII KYOKO , NOZAKI KOICHI , YOSHIOKA HIROSHI , KOYAMA YOSHIHISA , UDO SHINJI , AOYANAGI HIDETOMO , MIYATAKE SHINICHI , MORINO MAKOTO , HOSHIDA AKIHIKO
IPC分类号： G11C11/401 , G11C5/02 , H01L27/108
摘要： PURPOSE:To provide large storage capacity while attaining stabilized and high speed operation with a small area. CONSTITUTION:A DRAM cell is composed of a memory matrix with matrix- shaped arrangement and plural sets of sense amplifiers, provided with a selecting means for transmitting or stopping to transmit a signal from the respective sense amplifiers 2 and a Y selection line 1 transferring a selecting signal and a decoding circuit for selection is arranged almost in the middle part of the Y selection line 1. Respective X, Y address buffers are adjacent to the position nearer to the mid section of a chip than respective X, Y redundant circuits. A generating circuit for a reference voltage is arranged nearer to the end part of the chip than an output buffer circuit and a selecting circuit for relieving each redundant line in each memory matrix is arranged adjacently in every objective memory matrix. A part of wiring in the amplifier 2 is composed of the same wiring layer as that of the Y selection line 1 and the Y selection line passes through the spacing of the sense amplifier group. A shared MOS 5 and a data line precharging MOS 6 have the same specification of the quantity of impurity ion implantation and ion species as that of the memory cell.

78. 发明专利

JPH05307880A 失效
公开(公告)号：JPH05307880A
公开(公告)日：1993-11-19
申请号：JP13781992
申请日：1992-04-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , MIYAMOTO EIJI , NOZOE ATSUSHI , YOSHIOKA HIROSHI
IPC分类号： G11C11/407 , G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE:To shorten a time detecting leakage between STC cells by providing a means holding plural adjacent word lines forming the gate electrodes of serial parasitic MOSs in a selection state simultaneously. CONSTITUTION:L level information is written in the STC cell CO and H level information is written in the STC C1 at a normal memory mode. Then, setting a leakage between cells detection mode, the word Lines WL2, WL3 are made an H level simultaneously. When the word lines WL2, WL3 become the H level also, since the parasitic MOS-MO and M1 are turned on simultaneously, the leakage of charge from the STC cell 1 of the H level to the STC cell of the L level is ended instantaneously. Then, returning to the memory operation mode again, when the charge of the STC cell CO and C1 are read, the occurrence of the leakage between the cells is detected. Thus, a selecting time required for 1000 second extent in a 16 MDRAM is reduced to 10 second extent.

79. 发明专利

JPH04263193A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04263193A
公开(公告)日：1992-09-18
申请号：JP4581591
申请日：1991-02-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , TSUNOSAKI MANABU , MIYAMOTO EIJI , NOZOE ATSUSHI , YOSHIOKA HIROSHI
IPC分类号： G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/50 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To set an internal power-supply voltage so as to be low according to an external power-supply voltage without being limited by a current supply ability by a method wherein the potential of the internal power-supply voltage is set at a nearly definite value against a change in the potential of the external power-supply potential in an ordinary operation mode and it is changed according to a change in the potential in a prescribed test mode. CONSTITUTION:A dynamic RAM is constituted of a timing generation circuit TG and of an internal logic circuit LC which includes a memory array and its peripheral circuit. External power-supply voltages VCC and VSS are supplied to the circuit LC. At a voltage conversion circuit VC, the potential of an internal power-supply voltage VCL is fixed to a standard value when the potential of the VCC is within a prescribed range; it is proportional to the potential of the VCC and is changed so as to have a prescribed potential difference in a test mode where the VCC exceeds a prescribed value. Thereby, it is possible to accurately test an operation margin without being limited by a current supply ability.

80. 发明专利

JPH04258161A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04258161A
公开(公告)日：1992-09-14
申请号：JP4095491
申请日：1991-02-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHII KYOKO , MIYATAKE SHINICHI , TAKAHASHI TSUTOMU , UDO SHINJI , YOSHIOKA HIROSHI , TAKANO MITSUHIRO , MORINO MAKOTO
IPC分类号： H01L21/822 , G11C5/14 , G11C7/06 , G11C8/12 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent an irregularity in a leakage current of a memory cell due to a reduction in a power source noise and an irregularity in heat generation by providing a plurality of internal step-down circuits for forming an operating voltage of a sense amplifier upon reception of a power source voltage from an exterior corresponding to memory blocks one by one. CONSTITUTION:An X decoder 3 interprets an address signal having 9 bits X0-X9, and selects one word line. When an X address signal is fetched in synchronizm with a row address strobe signal RAS, an X series is selected. The word lines are selected one by one in each memory block, and one memory mat as indicated by a shade and one sense amplifier are operated. Internal step-down circuits 8 each for forming an operating voltage are respectively provided in the blocks corresponding to selection of the word line and dispersing operation of the amplifier. Thus, it prevents generation of noise of a high level due to flow of a large current concentrically to special wirings.

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