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71. 发明专利

JP2000187978A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000187978A
公开(公告)日：2000-07-04
申请号：JP36556398
申请日：1998-12-22
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SAKATA TAKESHI , IDE SEIHACHI , TAKAHASHI TSUTOMU , NAGASHIMA YASUSHI
IPC分类号： G11C11/407 , G11C11/401 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that an area of this sub-word driver is reduced in designing of the layout of the sub-word driver, and there is no possibility of that non-selection sub-word lines from which a main word line is selected is lifted up at the time of reset. SOLUTION: This device is 256Mb SDRAM(synchronous dynamic RAM) constituted of four banks, one PMOS transistor MP* and one NMOS transistor MN* connected respectively to main word lines MW* (*: arbitrary numeral) B are provided in a sub-word driver SWD of direct peripheral circuits corresponding to each memory array bank, further, a NMOS transistor MN* connected to a selection line FX*B is provided, the device is constituted so that the NMOS transistor MN* is shared by two sub-word drivers SWD, and the selection line FX*B is rest after reset of the sub-word line SWL* in timing.

72. 发明专利

JP2000124415A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JP2000124415A
公开(公告)日：2000-04-28
申请号：JP29056798
申请日：1998-10-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SAKAMOTO TATSUYA , SUZUKI YUKIE , ARAI KOJI , NAGASHIMA YASUSHI
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor memory device of layout technique, where a sense amplifier can be made to operate at a high speed reducing an increase in the area of the sense amplifier to an irreducible minimum through a sense amplifier driver dispersed installation method. SOLUTION: A four-bank 256 Mbit DRAM is composed of a four-bank memory cell array region, an array controller region and a Y decoder region corresponding to the memory cell array region, and a common peripheral circuit region. NMOS transistors M3 and M4 in an N channel side sense amplifier circuit 14 and an NMOS transistor M1 in a pull-down side sense amplifier driver circuit 18 are laid out through a manner where the gates G of the NMOS transistors M3 and M4 are formed in the shape of a letter U, the NMOS transistor M1 is arranged between the gates G, furthermore the gate G of the NMOS transistor M1 is divided in two, and a part of a diffusion layer L is removed. A P channel is the same as above.

73. 发明专利

JPH11297924A SEMICONDUCTOR MODULE AND SOCKET AND MIXED INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11297924A
公开(公告)日：1999-10-29
申请号：JP12179898
申请日：1998-04-15
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI
IPC分类号： H01L23/32 , H01L25/04 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To reduce parasitic components by shortening the length of an electric wiring. SOLUTION: In a memory module 10, a chip 11 on whose main surface plural bumps 12 are projected is butted and fixed to the main surface of a holder 13 formed like a rectangular plate at the opposite side to the bump 12 group, and right and left parts 16 and 15 to be held are formed on the both short sides of the holder 13. An outside storage device is mounted by arranging the plural memory modules 10 on a wiring substrate, and holding the parts 16 and 15 to be held by holding parts. Thus, the outside terminal of a memory module can be constituted of each bump itself, and the parasitic capacity or inductance of the memory module can be excluded. Also, the distortion of an electric signal waveform can be suppressed in the outside storage device using the memory module.

74. 发明专利

JPH09245486A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09245486A
公开(公告)日：1997-09-19
申请号：JP7322496
申请日：1996-03-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , NARUI SEIJI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To achieve a lower power consumption of a shadow RAM or the like by curtailing a required current especially in a recall mode and in a refreshing mode of the shadow RAM or the like. SOLUTION: A pair of memory arrays ARY0 and ARY1 is so arranged to be alternately made active selectively and sequentially and sense amplifiers SA0 and SA1 are so arranged to be selectively made ready with the supply of a power source voltage VCC or a ground voltage VSS to common source wires CSP0 and CSN0 or CSP1 and CSN1 corresponding to the pair of memory arrays ARY0 and ARY1. Short-circuiting switches P1 and N1 are provided respectively between the common source lines CSP0 and CSP1 and CSN0 and CSN1 to be temporarily turned ON until a corresponding sense amplifier SA0 or SA1 is made ready after the operation of selecting the word lines.

75. 发明专利

JPH098247A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH098247A
公开(公告)日：1997-01-10
申请号：JP17429695
申请日：1995-06-15
申请人： HITACHI LTD
发明人： HASEGAWA MASATOSHI , KAJITANI KAZUHIKO , TAKEUCHI MIKI , MATSUNO KATSUMI , NAGASHIMA YASUSHI
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE: To improve usefulness of a semiconductor storage device by programmably setting a nonvolatile section and volatile section of the storage device in corresponding to the kind of data to be handled. CONSTITUTION: A semiconductor storage device is constituted so that the storage device can have such a large storage capacity as 1G bits as a whole and, for such an application that access is made 8 by 8 bits, the storage device can be utilized as a storage device of about 128 M bytes. The plate voltage VPL supplied to the plate electrode of each of 64 memory mats is adjusted so that such a voltage as 0V of VSS can be set to such an intermediate voltage of VCC /2. The eight memory mats (hatched mats) are operated as an ordinary DRAM by setting their voltages VPL to VPL=VSS and used as a volatile area. The remaining memory mats are operated as a FERAM by setting their voltages VPL to VPL=VCC /2 and used as a nonvolatile area.

76. 发明专利

JP2511941B2 失效
公开(公告)号：JP2511941B2
公开(公告)日：1996-07-03
申请号：JP5881087
申请日：1987-03-16
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI
IPC分类号： G06F12/02 , G06F12/04 , G11C11/34 , G11C11/401

77. 发明专利

JPH04295691A ACTIVATION BYTE SELECTION SYSTEM AND SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04295691A
公开(公告)日：1992-10-20
申请号：JP6149091
申请日：1991-03-26
申请人： HITACHI LTD
发明人： HAMAMOTO RIYOUTA , NAGASHIMA YASUSHI
IPC分类号： G06F12/06 , G11C11/401
摘要： PURPOSE:To provide a technique which can remove a peripheral circuit used to select an activation byte for a semiconductor memory device to and from which a data of a plurality of bytes can be input and output. CONSTITUTION:Activation byte information which is used to indicate the number of bytes to be activated and their positions is added to an address signal for a dynamic RAM 30 which has been arranged in an address signal for a microcomputer 20; the number of activation bytes and their positions can be selected on the basis of activation byte information ABC included in the address signal. Thereby, a peripheral circuit used to select activation bytes for the dynamic RAM 30 to and from which a data of a plurality of bytes can be input and output can be omitted form the outside of the dynamic RAM 30, i.e., from a board on which the dynamic RAM 30 is mounted. As a result, the title system can be simplified.

78. 发明专利

JPH03296988A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03296988A
公开(公告)日：1991-12-27
申请号：JP9892690
申请日：1990-04-13
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI , MATSUMOTO YOSHINORI
IPC分类号： G11C11/409 , G11C11/401
摘要： PURPOSE:To contrive a reduction of chip occupancy area in a differential amplifier circuit by providing the amplifier circuit having 1st and 2nd current mirror loads to connect gate electrodes in common to each drain electrode of a pair of differential input transistors. CONSTITUTION:The differential amplifier circuit 50 is constituted of the 1st current mirror load 51 wherein the gate electrode is connected in common to the drain electrode of the differential input transistor Q11 of one side and the 2nd current mirror load 52 wherein the gate electrode is connected in common to the drain electrode of another differential input transistor Q12. So, the ratio of conductances for current mirror load of one side and for that of another side each other becomes constant whichever input level for the differential input is relatively higher, then, similar amplitudes for mutually compensated outputs can be obtained in either normal/inverse state of differential input signal. Thus, a stabilization of mutually compensated output for the differential amplifier circuit 50 can be obtained without increasing the area for chip.

79. 发明专利

JPH03291741A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH03291741A
公开(公告)日：1991-12-20
申请号：JP9433890
申请日：1990-04-10
申请人： HITACHI LTD
发明人： KITANO JUN , NISHIMOTO KENJI , NAGASHIMA YASUSHI , HATANO SUSUMU , OOISHI KANJI
IPC分类号： G06F12/08 , G11C11/401
摘要： PURPOSE:To reduce the width of bus to connect circuit blocks by dividing the first and second circuit blocks into plural sub blocks to get the same bit width and close arranging the correspondent sub blocks. CONSTITUTION:A block buffer is divided into a sub block 1 and a sub block 2. Corresponding to this division and the data of high-order 2 bytes X 4 words in charge of the sub block buffer 1, block way #0-#3 of the sub data array 1 are also divided into the sub blocks corresponding to the high-order 2 bytes X4 words. Similarly corresponding to the data of a low order 2 bytes X 4 words in charge of the sub block buffer 2, block ways #0-#3 of the sub data array 1 are also divided into the sub blocks corresponding to the low order 2 bytes X 4 words. In the buffer 1, the correspondent array 1 is close arranged and in the buffer 2, the correspondent array 2 is close arranged. Thus, the practical bus width can be reduced to half like 64 bits.

80. 发明专利

JPH03278145A SHARED MEMORY MANAGING DEVICE AND SHARED MEMORY 失效
公开(公告)号：JPH03278145A
公开(公告)日：1991-12-09
申请号：JP15246090
申请日：1990-06-11
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI
IPC分类号： D02J1/22 , G06F9/52 , G06F12/00 , G06F13/18 , G06F15/16 , G06F15/177
摘要： PURPOSE:To enhance the use efficiency of a bus in a multi-processor system provided with a shared memory, and to improve the throughput of the system by outputting a signal for showing an invalid access from an access managing part, in the case there is an invalid access to a management area. CONSTITUTION:An access managing part 2 in a shared memory 10 or a memory managing device decides valid/invalid of an access to a management area 1b and outputs a response signal, therefore, it will suffice that a microprocessor outputs a bus lock signal only at the time of read and write to the management area 1b. In other case, even if the bus remains open, an invalid access of the shared memory 10 can be avoided, and the other processor can access an output area 1a of the shared memory 10 by using a free cycle of the bus. In such a way, the use efficiency of the bus is enhanced and the throughput of the system can be improved.

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