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71. 发明申请

US20060121677A1 Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法
公开(公告)号：US20060121677A1
公开(公告)日：2006-06-08
申请号：US11003275
申请日：2004-12-03
申请人： Kunal Parekh , John Zahurak
发明人： Kunal Parekh , John Zahurak
IPC分类号： H01L21/8234
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823425 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
摘要翻译：本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与在晶体管的栅极附近的各向异性蚀刻的侧壁间隔开。

72. 发明申请

US20060043468A1 Stepped gate configuration for non-volatile memory 审中-公开
公开(公告)号：US20060043468A1
公开(公告)日：2006-03-02
申请号：US11257843
申请日：2005-10-25
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , G11C16/0416 , G11C16/0483 , H01L29/40117
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

73. 发明申请

US20050255701A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20050255701A1
公开(公告)日：2005-11-17
申请号：US10848247
申请日：2004-05-17
申请人： Werner Juengling , Steven McDonald , Kunal Parekh
发明人： Werner Juengling , Steven McDonald , Kunal Parekh
IPC分类号： H01L21/302 , H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.
摘要翻译：本发明包括一种方法，通过该方法制造半导体结构的保险丝盒以在其中延伸的保险丝上具有基本均匀的层。在具体方面，本发明包括这样的方法，其中与保险丝盒区域同时进行与接合焊盘和再分配层的制造和图案相关联的一个或多个处理步骤，以形成和/或去除直接位于保险丝盒区域上方的材料。

74. 发明申请

US20050173745A1 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 有权
标题翻译：电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法
公开(公告)号：US20050173745A1
公开(公告)日：2005-08-11
申请号：US11074107
申请日：2005-03-07
申请人： Kunal Parekh , John Zahurak
发明人： Kunal Parekh , John Zahurak
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10811 , H01L27/10855 , H01L28/84 , Y10S438/964
摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.
摘要翻译：本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。

75. 发明申请

US20050162963A1 Memory redundancy programming 失效
标题翻译：内存冗余编程
公开(公告)号：US20050162963A1
公开(公告)日：2005-07-28
申请号：US10764954
申请日：2004-01-26
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： G11C11/34 , G11C29/00
CPC分类号： G11C17/18 , G11C29/789
摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.
摘要翻译：提供了一种用于执行冗余编程的方法和装置。本发明的系统包括用于执行存储器测试的设备测试单元。该系统还包括可操作地耦合到设备测试单元的存储器件。存储器件包括存取晶体管，其包括电荷捕获区域。在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。存储器件还包括存储器元件和与存储器元件相关联的保险丝。响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。熔丝的状态可用于对存储元件进行编程或解除编程。

76. 发明申请

US20050030697A1 CAPACITOR STRUCTURE 失效
标题翻译：电容结构
公开(公告)号：US20050030697A1
公开(公告)日：2005-02-10
申请号：US10932503
申请日：2004-09-02
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L21/02 , H01L21/8242 , H01G4/30
CPC分类号： H01L27/10852 , H01L28/82
摘要： A capacitor is formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：电容器形成为具有大致凹入的形状并且具有可选的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

77. 发明申请

US20050009270A1 METHODS OF FORMING MEMORY CIRCUITRY 失效
标题翻译：形成记忆电路的方法
公开(公告)号：US20050009270A1
公开(公告)日：2005-01-13
申请号：US10615287
申请日：2003-07-07
申请人： Kunal Parekh , Byron Burgess
发明人： Kunal Parekh , Byron Burgess
IPC分类号： G11C11/00 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
摘要翻译：本发明包括形成存储器电路的方法。在一个实施方案中，半导体衬底包括一对在其间接收的位节点的字线。在位节点上的绝缘材料内形成位节点接触开口。牺牲性封堵材料形成在一对字线之间的位节点接触开口内。牺牲性封堵材料从一对字线对之间的位节点接触开口移除，并由与位节点电连接的导电材料代替。之后，将导电材料形成为位线。

78. 发明授权

US06740923B2 Capacitor structure 有权
标题翻译：电容结构
公开(公告)号：US06740923B2
公开(公告)日：2004-05-25
申请号：US10145250
申请日：2002-05-14
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L31119
CPC分类号： H01L27/10852 , H01L28/82
摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：本发明涉及一种电容器的制造，该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

79. 发明授权

US06682984B1 Method of making a concave capacitor 有权
标题翻译：制作凹电容器的方法
公开(公告)号：US06682984B1
公开(公告)日：2004-01-27
申请号：US09535483
申请日：2000-03-24
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L2120
CPC分类号： H01L27/10852 , H01L28/82
摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：本发明涉及一种电容器的制造，该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

80. 发明授权

US06309973B1 Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
标题翻译：形成导电投影的半导体处理方法和增加对准公差的方法
公开(公告)号：US06309973B1
公开(公告)日：2001-10-30
申请号：US09507193
申请日：2000-02-18
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21302
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a, portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.
摘要翻译：描述形成导电突起的半导体加工方法和增加对准公差的方法。在一个实施方案中，导电突起形成在衬底表面区域上，并且包括与其连接的上表面和侧表面以限定拐角区域。导电突起的角区域随后被倒角以增加相对于其的对准公差。在另一实施方案中，导电插塞形成在一对导线之间的衬底节点位置之上并且具有最上表面。导电插塞的材料被不均匀地移除以限定第二最上表面，其中至少一部分的表面布置在高于导电线的高度上。在一个方面，可以通过刻蚀导电插塞去除导电插塞材料。在另一方面，导电插塞材料用掺杂剂不均匀掺杂，并且以比含有较低浓度掺杂剂的插塞材料更大的速率蚀刻含有较大浓度掺杂剂的导电插塞材料。

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