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71. 发明授权

US06335884B1 Semiconductor memory device and defect remedying method thereof 有权
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US06335884B1
公开(公告)日：2002-01-01
申请号：US09714268
申请日：2000-11-17
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C1300
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
摘要翻译：这里公开了一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由交叉区域。由于外围电路布置在芯片的中心部分的这种结构，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的大容量。

72. 发明授权

US5712859A Semiconductor integrated circuit 失效
公开(公告)号：US5712859A
公开(公告)日：1998-01-27
申请号：US707316
申请日：1996-09-03
申请人： Ryoichi Hori , Kiyoo Itoh , Hitoshi Tanaka
发明人： Ryoichi Hori , Kiyoo Itoh , Hitoshi Tanaka
IPC分类号： G01R31/30 , G05F1/46 , G11C5/14 , G11C29/50 , H01L27/02 , G01R31/317
CPC分类号： G11C29/50 , G01R31/30 , G05F1/465 , G11C5/145 , G11C5/147 , H01L27/0218
摘要： In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.

73. 发明授权

US5614847A Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US5614847A
公开(公告)日：1997-03-25
申请号：US294055
申请日：1994-08-24
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

74. 发明授权

US5579256A Semiconductor memory device and defect remedying method thereof 失效
公开(公告)号：US5579256A
公开(公告)日：1996-11-26
申请号：US455411
申请日：1995-05-31
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C5/00 , G11C5/02 , G11C11/406 , H01L23/485
CPC分类号： H01L24/05 , G11C11/406 , G11C5/025 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L24/45 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01033 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , Y10S257/908
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

75. 发明授权

US5272393A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5272393A
公开(公告)日：1993-12-21
申请号：US790065
申请日：1991-11-12
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , H03K3/01 , H03K5/22
CPC分类号： H03K17/693 , G05F1/465
摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.
摘要翻译：在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。

76. 发明授权

US4930112A Semiconductor device having a voltage limiter 失效
标题翻译：具有限压器的半导体器件
公开(公告)号：US4930112A
公开(公告)日：1990-05-29
申请号：US934546
申请日：1986-11-24
申请人： Hitoshi Tanaka , Ryoichi Hori , Kiyoo Itoh , Katsutaka Kimura , Katsuhiro Shimohigashi
发明人： Hitoshi Tanaka , Ryoichi Hori , Kiyoo Itoh , Katsutaka Kimura , Katsuhiro Shimohigashi
IPC分类号： G11C11/407 , G05F1/46 , G11C11/401 , G11C11/4074 , G11C11/409
CPC分类号： G05F1/465 , G11C11/4074
摘要： A semiconductor device comprising a plurality of circuits driven by at least one external power source, and at least one voltage converter transforming the voltage of the external power source into another voltage. At least a part of the plurality of circuits are driven by the output voltage of the at least one voltage converter, which is provided with a controller for controlling its load driving power, corresponding to the operation of the part of the plurality of circuits. The voltage converter includes a voltage limiter which is used exclusively for each of the different natures of the loads, and its operation and load driving power are controlled, depending on the operations of each of the loads.
摘要翻译：一种半导体器件，包括由至少一个外部电源驱动的多个电路和至少一个将外部电源的电压转换成另一电压的电压转换器。所述多个电路的至少一部分由所述至少一个电压转换器的输出电压驱动，所述至少一个电压转换器的输出电压与所述多个电路的所述部分的操作相对应地设置有用于控制其负载驱动功率的控制器。电压转换器包括专用于负载的不同性质的电压限制器，并且根据每个负载的操作来控制其操作和负载驱动功率。

77. 发明授权

US4894696A Dynamic random access memory having a trench capacitor 失效
标题翻译：具有沟槽电容器的动态随机存取存储器
公开(公告)号：US4894696A
公开(公告)日：1990-01-16
申请号：US938967
申请日：1986-12-08
申请人： Eiji Takeda , Kiyoo Itoh , Ryoichi Hori , Katsuhiro Shimohigashi , Katsutaka Kimura
发明人： Eiji Takeda , Kiyoo Itoh , Ryoichi Hori , Katsuhiro Shimohigashi , Katsutaka Kimura
IPC分类号： H01L27/10 , G11C11/34 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , Y10S257/90
摘要： A very highly integrated semiconductor memory which enables the dynamic random access memory to develop less soft error and to eliminate margin for aligning the masks, that hinders the device from being highly integrated. The memory cell capacitor is constituted by a trench which is provided at a position defined by an insulator formed on the side of gate electrode of a MOS transistor that constitutes the memory cell. Therefore, the MOS transistor and the trench capacitor are self-aligned, and no margin is required for alignment.
摘要翻译：一种非常高度集成的半导体存储器，其使得动态随机存取存储器能够开发更少的软错误并消除对准掩模的余量，这妨碍了器件的高度集成。存储单元电容器由设置在由形成在构成存储单元的MOS晶体管的栅极侧的绝缘体限定的位置处的沟槽构成。因此，MOS晶体管和沟槽电容器是自对准的，并且不需要用于对准的余量。

78. 发明授权

US4739497A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4739497A
公开(公告)日：1988-04-19
申请号：US651453
申请日：1984-09-17
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G11C5/02 , G11C5/06 , G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/108 , G11C11/40 , G11C13/00
CPC分类号： G11C5/025 , G11C11/4087 , G11C11/4096 , G11C11/4097 , G11C5/06 , G11C5/063 , G11C7/10 , G11C8/12 , H01L27/10805
摘要： A semiconductor memory is provided which includes a plurality of data lines, a plurality of word lines which are arranged so as to intersect the plurality of data lines, and a plurality of memory cells which are respectively disposed at intersection points between the plurality of data lines and the plurality of word lines. A row decoder selects at least one from among the plurality of word lines, while a column decoder generates a signal for connecting one of the plurality of data lines to an input/output line. A plurality of wiring leads are also provided which are formed of a conductor layer different from conductor layers constituting the plurality of data lines and the plurality of word lines and which are arranged so as to intersect the plurality of data lines.
摘要翻译：提供一种半导体存储器，其包括多条数据线，与多条数据线相交配置的多条字线，以及分别设置在多条数据线之间的交点处的多条存储器单元和多个字线。行解码器从多个字线中选择至少一个，而列解码器产生用于将多条数据线之一连接到输入/输出线的信号。还提供了多个布线引线，其由与构成多条数据线和多条字线的导体层不同的导体层形成，并且被布置成与多条数据线相交。

79. 发明授权

US4691304A Semiconductor device having an arrangement for preventing operational errors 失效
标题翻译：具有用于防止操作错误的装置的半导体装置
公开(公告)号：US4691304A
公开(公告)日：1987-09-01
申请号：US739092
申请日：1985-05-30
申请人： Ryoichi Hori , Kiyoo Itoh
发明人： Ryoichi Hori , Kiyoo Itoh
IPC分类号： G11C11/413 , G05F3/20 , G06F1/26 , G11C7/02 , G11C11/407 , G11C11/408 , H01L27/02 , H02M3/07 , G11C7/00
CPC分类号： H01L27/0218 , G05F3/205 , H02M3/07
摘要： This invention relates to a semiconductor device formed on a semiconductor chip which is provided with at least a voltage transformation arrangement for transforming an external power supply voltage into an internal power supply voltage. At least a portion of circuits formed in the chip operate by using the internal power supply voltage rather than the external power supply voltage. Semiconductor devices, in particular DRAMs (dynamic random access memories), in which said internal power supply voltage is supplied are controlled so that the starting time of the internal power supply voltage at the moment of the switch-on of the external power supply is later than the starting time of the external power supply voltage, and/or the time necessary for the internal power supply voltage to increase to a predetermined operational level at said moment is longer than that required for said external power supply voltage to increase to a predetermined operational level.
摘要翻译：本发明涉及形成在半导体芯片上的半导体器件，该半导体器件至少具有用于将外部电源电压变换为内部电源电压的电压变换装置。芯片中形成的至少一部分电路通过使用内部电源电压而不是外部电源电压来工作。控制提供所述内部电源电压的半导体装置，特别是DRAM（动态随机存取存储器），使得外部电源的接通时的内部电源电压的起始时间稍晚比外部电源电压的开始时间和/或内部电源电压在所述时刻增加到预定操作电平所需的时间长于所述外部电源电压所需的时间增加到预定的操作水平。

80. 发明授权

US4590588A Monolithic semiconductor memory 失效
标题翻译：单片半导体存储器
公开(公告)号：US4590588A
公开(公告)日：1986-05-20
申请号：US515519
申请日：1983-07-20
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G11C5/06 , G11C7/10 , G11C7/18 , G11C5/02
CPC分类号： G11C7/18 , G11C5/063 , G11C7/10 , G11C7/1006
摘要： A semiconductor memory is disclosed having data lines divided lengthwise, which data lines cross word lines in a memory cell array and are selectively coupled to memory cells. A plurality of second data lines are arranged, one for each of predetermined groups of the data lines, to exchange data through first switches. Also one or more third data lines are arranged orthogonally to the second data lines to exchange data with the second data lines through second switches. Read/write controllers are coupled to the third data lines. Data is read and written for desired memory cells by selective drive of the word lines and the first and second switches.
摘要翻译：公开了半导体存储器，其具有纵向分割的数据线，哪些数据线与存储单元阵列中的字线交叉并且选择性地耦合到存储器单元。布置多个第二数据线，每个数据线的预定组中的每一个通过第一开关交换数据。还有一个或多个第三数据线与第二数据线正交地布置，以通过第二开关与第二数据线交换数据。读/写控制器耦合到第三条数据线。通过选择性地驱动字线和第一和第二开关来读取和写入所需存储单元的数据。

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