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71. 发明授权

US6115310A Wordline activation delay monitor using sample wordline located in data-storing array 有权
标题翻译：字线激活延迟监视器使用位于数据存储阵列中的示例字线
公开(公告)号：US6115310A
公开(公告)日：2000-09-05
申请号：US225343
申请日：1999-01-05
申请人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
发明人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C8/08 , G11C8/14 , G11C8/18 , G11C11/408 , G11C11/4091 , G11C7/02
CPC分类号： G11C8/18 , G11C11/408 , G11C11/4091 , G11C8/14
摘要： A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.
摘要翻译：本文公开了一种字线激活延迟监视器电路，其包括位于存储器的数据存储阵列内的采样字线，其中采样字线由存储器内具有基本相同结构或位置的电路选择或激活，该电路选择或激活数据存储阵列的字线。公开了一种电路，其通过激活位于第二子阵列组的数据存储阵列内的采样字线来确定存储器内的第一子阵列组的字线激活延迟。还公开了相应的方法。

72. 发明授权

US6038634A Intra-unit block addressing system for memory 失效
标题翻译：内存单元块寻址系统
公开(公告)号：US6038634A
公开(公告)日：2000-03-14
申请号：US17017
申请日：1998-02-02
申请人： L. Brian Ji , Toshiaki Kirihata
发明人： L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C11/407 , G11C8/10 , G11C11/401 , G11C11/408 , G11C11/409 , G06F12/06
CPC分类号： G11C8/10
摘要： A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which accesses storage locations of the first and second storage units according to first and second selection signals conducted from the outer extremities of the double memory unit to selected row locations. The blocks at corresponding distances from the outer extremities are numbered differently such that the sum of lengths of signal travel of the first and second selection signals to the numbered blocks remains relatively constant regardless of the block number which is selected for access.
摘要翻译：本文公开了一种用于稳定与双存储器单元的第一和第二存储单元内的块访问相关的电流耗散，电压降和加热效应的系统。该系统包括位于第一和第二存储单元之间的行选择单元，其根据从双存储器单元的外端传输到所选行位置的第一和第二选择信号访问第一和第二存储单元的存储位置。与外部相对应的距离的块以不同的方式编号，使得第一和第二选择信号到编号的块的信号行程的长度之和保持相对恒定，而不管选择用于访问的块号。

73. 发明授权

US5978931A Variable domain redundancy replacement configuration for a memory device 失效
标题翻译：存储设备的可变域冗余替换配置
公开(公告)号：US5978931A
公开(公告)日：1999-11-02
申请号：US895061
申请日：1997-07-16
申请人： Toshiaki Kirihata , Garbiel Daniel , Jean-Marc Dortu , Karl-Peter Pfefferl
发明人： Toshiaki Kirihata , Garbiel Daniel , Jean-Marc Dortu , Karl-Peter Pfefferl
IPC分类号： G11C29/44 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/804 , G11C29/808
摘要： A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.
摘要翻译：描述了具有可变域冗余替换（VDRR）布置的容错存储器件。存储器件包括：多个主存储器阵列; 多个域具有与另一域共同的一个域的至少部分以形成重叠域区域，并且至少一个域重叠至少两个主存储器阵列的部分; 冗余单元，耦合到每个域，用于替换每个域内包含的故障; 控制电路，用于将要被所述冗余单元替换的所述域内的至少一个故障引导到所述冗余单元，其中所述一个域的至少一个其它故障被耦合到所述域中的另一个的所述冗余单元替换，如果至少另一个故障位于重叠域区域内。支持主存储器阵列的每个冗余单元包括多个冗余元件。与传统的固定域冗余替换方案不同，RU被分配给至少两个可变域，其中域的至少一部分与另一个域的共同。 VDRR使得可以选择最有效的域，特别是用于修复随机故障的较小域或用于修复集群故障的较大域。

74. 发明授权

US5831913A Method of making a memory fault-tolerant using a variable size redundancy replacement configuration 失效
标题翻译：使用可变大小的冗余替换配置来创建容错的方法
公开(公告)号：US5831913A
公开(公告)日：1998-11-03
申请号：US825948
申请日：1997-03-31
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/804 , G11C29/808
摘要： A method of making a memory fault-tolerant through the use of a variable size redundancy replacement (VSRR) circuit arrangement. A redundancy array supporting the primary arrays forming the memory includes a plurality of variable size redundancy units, each of which encompassing a plurality of redundant elements. The redundant units used for repairing faults in the memory are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This method significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
摘要翻译：通过使用可变尺寸冗余替换（VSRR）电路布置来使存储器容错的方法。支持形成存储器的主阵列的冗余阵列包括多个可变大小的冗余单元，每个冗余单元包括多个冗余元件。用于修复存储器故障的冗余单元是独立控制的。维修单元内的所有冗余元件优选同时更换。冗余单元中的冗余元件通过解码地址线来控制。表征此配置的可变大小使得可以选择最有效的冗余单元，特别是最接近要替换的故障群集大小的冗余单元。该方法显着降低了增加冗余元件和控制电路所产生的开销，同时提高了访问速度并降低了功耗。最后，由优先级解码器控制的容错块冗余使得可以使用VSRR单元来修复块冗余中的故障，在其用于替换存储器内的有缺陷块之前。

75. 发明授权

US5745431A Address transition detector (ATD) for power conservation 失效
标题翻译：地址转换检测器（ATD）用于节能
公开(公告)号：US5745431A
公开(公告)日：1998-04-28
申请号：US583263
申请日：1996-01-05
申请人： Dale Edward Pontius , Steven William Tomashot , Toshiaki Kirihata , Robert Henry Kruggel
发明人： Dale Edward Pontius , Steven William Tomashot , Toshiaki Kirihata , Robert Henry Kruggel
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the address input signals input to the address decode circuit with the control signal.
摘要翻译：一种用于接收地址输入信号的地址解码电路，包括用于检测地址输入信号变化的装置，以及响应于所检测到的地址输入信号的变化而产生控制信号的装置。选通机构通过控制信号将输入到地址解码电路的地址输入信号中的至少一个地址位置1。

76. 发明授权

US5541887A Multiple port cells with improved testability 失效
标题翻译：多端口单元具有改进的可测试性
公开(公告)号：US5541887A
公开(公告)日：1996-07-30
申请号：US375025
申请日：1995-01-19
申请人： Sang H. Dhong , Wei Hwang , Toshiaki Kirihata
发明人： Sang H. Dhong , Wei Hwang , Toshiaki Kirihata
IPC分类号： G11C8/16 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C8/16
摘要： Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two or more ports of that cell, as may be encountered during rigorous testing procedures. Memory structure, particularly that of the input port circuits, is simplified and operational speed is enhanced since signal propagation through a comparator or logic circuit is avoided. Time required for testing of large memory arrays is also significantly reduced.
摘要翻译：施加到多端口存储器单元的相应输入端口的顺序终止写入使能脉冲对于在这些输入端口之间建立优先级是有效的，并且当在该单元的两个或更多个端口同时尝试写入操作时，向存储器单元提供无条件地明确的写入，如在严格的测试程序中可能遇到的。存储器结构，特别是输入端口电路的存储器结构被简化，并且由于避免了通过比较器或逻辑电路的信号传播，因此提高了操作速度。大型存储器阵列测试所需的时间也大大减少。

77. 发明授权

US08754412B2 Intra die variation monitor using through-silicon via 失效
标题翻译：使用硅片通孔的芯片内变形监测器
公开(公告)号：US08754412B2
公开(公告)日：2014-06-17
申请号：US13342226
申请日：2012-01-03
申请人： Xiaojun Yu , Anda C. Mocuta , Toshiaki Kirihata
发明人： Xiaojun Yu , Anda C. Mocuta , Toshiaki Kirihata
IPC分类号： H01L29/10
CPC分类号： H01L22/34 , H01L23/481 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.
摘要翻译：一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

78. 发明授权

US08120968B2 High voltage word line driver 失效
标题翻译：高电压字线驱动器
公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译：耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。字线耦合到一个或多个DRAM单元。源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

79. 发明申请

US20110199837A1 High Voltage Word Line Driver 失效
标题翻译：高电压字线驱动器
公开(公告)号：US20110199837A1
公开(公告)日：2011-08-18
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C8/08 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译：耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。字线耦合到一个或多个DRAM单元。源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

80. 发明授权

US07885138B2 Three dimensional twisted bitline architecture for multi-port memory 失效
标题翻译：用于多端口存储器的三维扭转位线架构
公开(公告)号：US07885138B2
公开(公告)日：2011-02-08
申请号：US11875173
申请日：2007-10-19
申请人： Hoki Kim , Toshiaki Kirihata
发明人： Hoki Kim , Toshiaki Kirihata
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/02 , G11C7/1075 , G11C7/18 , G11C11/412
摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
摘要翻译：本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

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