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71. 发明授权

US07247905B2 Offset vertical device 失效
标题翻译：偏移垂直装置
公开(公告)号：US07247905B2
公开(公告)日：2007-07-24
申请号：US10813352
申请日：2004-03-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

72. 发明申请

US20070047293A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 有权
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
申请人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
发明人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

73. 发明申请

US20060044692A1 Flying height compensation for up/down bit error rate trend difference 失效
标题翻译：飞高高度补偿上/下位误差率趋势差异
公开(公告)号：US20060044692A1
公开(公告)日：2006-03-02
申请号：US10933774
申请日：2004-09-02
申请人： Geng Wang , Sang Lee
发明人： Geng Wang , Sang Lee
IPC分类号： G11B5/60 , G11B15/64 , G11B17/32 , G11B21/20
CPC分类号： G11B5/58 , G11B5/6005 , G11B5/6082
摘要： A disk drive that has a plurality of heads coupled to one or more disks. The heads have air bearing surfaces that compensate for a radial crown and a radial camber of an adjacent disk to maintain a flying height at a relatively constant level across the disk surface. By way of example, the air bearing surfaces may have crown and camber sensitivities that are opposite in sign from the crown and camber sensitivities created by the disk. The opposite sensitivities offset the sensitivities of the disk to maintain an essentially constant flying height as the head moves across the surface of a disk.
摘要翻译：具有耦合到一个或多个盘的多个头的磁盘驱动器。头具有空气轴承表面，其补偿相邻盘的径向冠和径向弧形，以将浮动高度保持在跨越盘表面的相对恒定的水平。作为示例，空气轴承表面可以具有与表冠相反的表冠和弧度灵敏度，以及由盘产生的曲面灵敏度。当磁头移动穿过磁盘表面时，相反的灵敏度抵消磁盘的灵敏度以保持基本上恒定的飞行高度。

74. 发明授权

US10131794B2 Network copolymer crosslinked compositions and products comprising the same 有权
公开(公告)号：US10131794B2
公开(公告)日：2018-11-20
申请号：US12975885
申请日：2010-12-22
申请人： Ning Lu , Sigfredo Gonzalez , Ernie Silvestre , Geng Wang
发明人： Ning Lu , Sigfredo Gonzalez , Ernie Silvestre , Geng Wang
IPC分类号： A61K8/81 , A61Q19/00 , C09D4/00
摘要： The present invention provides for a household, agricultural, coating or personal care product composition containing the crosslinked reaction product of a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2═C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r and CH2═C(R3)C(O)OXa′(C2H4O)b′(C3H6O)c′(C4H8O)d′—SO3—Y) where R3=H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a, a′, b, b′, c, c′, d and d′ are 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).

75. 发明授权

US09484269B2 Structure and method to control bottom corner threshold in an SOI device 有权
标题翻译：在SOI器件中控制底角阈值的结构和方法
公开(公告)号：US09484269B2
公开(公告)日：2016-11-01
申请号：US12822492
申请日：2010-06-24
申请人： Joseph Ervin , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Joseph Ervin , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L27/12 , H01L21/8242 , H01L21/84 , H01L21/762 , H01L27/108
CPC分类号： H01L21/84 , H01L21/76237 , H01L27/10847 , H01L27/1203
摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.
摘要翻译：半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。

76. 发明授权

US09048339B2 Deep trench capacitor 有权
标题翻译：深沟槽电容器
公开(公告)号：US09048339B2
公开(公告)日：2015-06-02
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L27/108 , H01L27/12
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译：提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂散装衬底形成掩埋板。该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部，去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

77. 发明授权

US08936996B2 Structure and method for topography free SOI integration 有权
标题翻译：地形自由SOI集成的结构和方法
公开(公告)号：US08936996B2
公开(公告)日：2015-01-20
申请号：US12958429
申请日：2010-12-02
申请人： Ravi M. Todi , Joseph Ervin , Chengwen Pei , Geng Wang
发明人： Ravi M. Todi , Joseph Ervin , Chengwen Pei , Geng Wang
IPC分类号： H01L21/76 , H01L29/02 , H01L21/762
CPC分类号： H01L29/02 , H01L21/76254
摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.
摘要翻译：提供了包括具有特征的半导体氧化物层的半导体结构。具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。半导体氧化物层内的特征与有源半导体层的表面配合。

78. 发明授权

US08835994B2 Reduced corner leakage in SOI structure and method 有权
公开(公告)号：US08835994B2
公开(公告)日：2014-09-16
申请号：US12791372
申请日：2010-06-01
申请人： Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L29/786 , H01L27/12 , H01L21/84 , H01L29/66 , H01L27/108 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/1087 , H01L27/10873 , H01L27/1203 , H01L29/66181 , H01L29/78603 , H01L29/78609 , H01L29/78696 , H01L29/945
摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

79. 发明授权

US08669337B2 Network copolymer crosslinked compositions and methods of making the same 有权
标题翻译：网络共聚物交联组合物及其制备方法
公开(公告)号：US08669337B2
公开(公告)日：2014-03-11
申请号：US12646333
申请日：2009-12-23
申请人： Ning Lu , Sigfredo Gonzalez , Emie M. Silvestre , Geng Wang
发明人： Ning Lu , Sigfredo Gonzalez , Emie M. Silvestre , Geng Wang
IPC分类号： C08F230/02 , C08F220/38
CPC分类号： C08F220/38 , C08F228/02 , C08F230/02
摘要： The present invention is directed to a network composition having the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2═C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r where R3═H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100; c is 0 to about 100; d is 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and CH2═C(R3)C(O)OXa′(C2H4O)b′(C3H6O)c′(C4H8O)d′—SO3—Y) where R3═H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a′ is 0 to about 100; b′ is 0 to about 100; c′ is 0 to about 100; d′ is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).
摘要翻译：本发明涉及一种具有以下反应产物的网络组合物：（i）至少一种选自[CH2 = C（R3）C（O）OXa（C2H4O））的阴离子可聚合烯属不饱和单体（I） b（C 3 H 6 O）c（C 4 H 8 O）d] pP（O）（OY）q（OZ）r其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0〜100; b为0至约100; c为0至约100; d为0至约100; q为0〜2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; 和C 2 = C（R 3）C（O）O X a'（C 2 H 4 O）b'（C 3 H 6 O）c'（C 4 H 8 O）d-SO 3 -Y）其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0至约100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

80. 发明申请

US20140061793A1 SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY 有权
标题翻译：使用固体相外延片的子图形宽度FINFET
公开(公告)号：US20140061793A1
公开(公告)日：2014-03-06
申请号：US13597752
申请日：2012-08-29
申请人： Chengwen Pei , Kangguo Cheng , Joseph Ervin , Juntao Li , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Kangguo Cheng , Joseph Ervin , Juntao Li , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/12 , H01L29/06 , H01L21/336
CPC分类号： H01L27/0886 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/0657 , H01L29/0692 , H01L29/66795
摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.
摘要翻译：介电心轴结构形成在单晶半导体层上。非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

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