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71. 发明授权

US07640386B2 Systems and methods for providing memory modules with multiple hub devices 有权
标题翻译：为多个集线器设备提供内存模块的系统和方法
公开(公告)号：US07640386B2
公开(公告)日：2009-12-29
申请号：US11420046
申请日：2006-05-24
申请人： Paul W. Coteus , Warren E. Maule , Edward J. Seminaro , Robert B. Tremaine
发明人： Paul W. Coteus , Warren E. Maule , Edward J. Seminaro , Robert B. Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.
摘要翻译：为多个集线器设备提供内存模块的系统和方法。示例性系统包括具有存储器总线的级联互连存储器系统，存储器控制器和存储器模块。存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。存储器模块包括具有三个或更多个端口的第一集线器设备和具有三个或更多个端口的第二集线器设备。第一集线器设备上的第一端口经由存储器总线与存储器控制器通信，第一集线器设备上的第二端口与第一组存储器设备通信，第一集线器设备上的第三端口级联连接到第二集线器设备上的第一端口。第二集线器设备上的第二端口与第二组存储器设备通信，并且第二集线器设备上的第三端口支持与存储器系统中的后续集线器设备的级联连接。

72. 发明申请

US20090119443A1 METHODS FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS 失效
标题翻译：程序方向记忆访问模式的方法
公开(公告)号：US20090119443A1
公开(公告)日：2009-05-07
申请号：US12349269
申请日：2009-01-06
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/08
CPC分类号： G06F12/0607 , G06F12/10 , G06F13/28
摘要： Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
摘要翻译：用于程序定向存储器访问模式的系统和方法，包括具有存储器的存储器系统，存储器控制器和虚拟存储器管理系统。存储器包括被组织成一个或多个物理组的多个存储器件，可通过相关联的总线访问以传送数据和控制信息。存储器控制器接收并响应包含应用访问信息的存储器访问请求，以控制存储器内的访问模式和数据组织。响应于存储器访问请求包括访问一个或多个存储器设备。虚拟存储器管理系统包括：多个页表条目，用于将虚拟存储器地址映射到存储器中的实际地址; 响应于应用程序访问信息的指示状态，用于指示相关联的页面的实际存储器如何被物理地组织在存储器内; 以及用于将提示状态传送到存储器控制器的装置。

73. 发明申请

US20080270741A1 STRUCTURE FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS 失效
标题翻译：程序方向记忆访问模式的结构
公开(公告)号：US20080270741A1
公开(公告)日：2008-10-30
申请号：US12126747
申请日：2008-05-23
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0215 , G06F12/10 , G06F13/28
摘要： Design structures for program directed memory access patterns. A design structure is embodied in a machine readable medium used in a design process, the design structure including a computer memory system for storing and retrieving data. The memory system includes a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
摘要翻译：程序定向内存访问模式的设计结构。设计结构体现在在设计过程中使用的机器可读介质中，该设计结构包括用于存储和检索数据的计算机存储器系统。存储器系统包括存储器，存储器控制器和虚拟存储器管理系统。存储器包括被组织成一个或多个物理组的多个存储器件，可通过相关联的总线访问以传送数据和控制信息。存储器控制器接收并响应包含应用访问信息的存储器访问请求，以控制存储器内的访问模式和数据组织。响应于存储器访问请求包括访问一个或多个存储器设备。虚拟存储器管理系统包括：多个页表条目，用于将虚拟存储器地址映射到存储器中的实际地址; 响应于应用程序访问信息的指示状态，用于指示相关联的页面的实际存储器如何被物理地组织在存储器内; 以及用于将提示状态传送到存储器控制器的装置。

74. 发明授权

US06665787B2 Very high speed page operations in indirect accessed memory systems 失效
公开(公告)号：US06665787B2
公开(公告)日：2003-12-16
申请号：US09795414
申请日：2001-02-28
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith, III , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F1208
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

75. 发明授权

US09086957B2 Requesting a memory space by a memory controller 有权
标题翻译：通过内存控制器请求内存空间
公开(公告)号：US09086957B2
公开(公告)日：2015-07-21
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F3/06 , G06F11/22 , G06F12/08
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

76. 发明授权

US08692561B2 Implementing chip to chip calibration within a TSV stack 有权
标题翻译：在TSV堆栈内实现芯片到芯片校准
公开(公告)号：US08692561B2
公开(公告)日：2014-04-08
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： G01R35/00
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

77. 发明申请

US20140040576A1 REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER 有权
标题翻译：由记忆控制器请求记忆空间
公开(公告)号：US20140040576A1
公开(公告)日：2014-02-06
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/16
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

78. 发明授权

US08618960B1 Selective recompression of a string compressed by a plurality of diverse lossless compression techniques 失效
公开(公告)号：US08618960B1
公开(公告)日：2013-12-31
申请号：US13587559
申请日：2012-08-16
申请人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
发明人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
IPC分类号： H03M7/34
CPC分类号： H03M7/3059 , H03M7/6047 , H03M7/607
摘要： In response to receiving an input string to be compressed, a plurality of diverse lossless compression techniques are applied to the input string to obtain a plurality of compressed strings. The plurality of diverse lossless compression techniques include a template-based compression technique and a non-template-based compression technique. A most compressed string among the plurality of compressed strings is selected. A determination is made regarding whether or not the most compressed string was obtained by application of the template-based compression technique. In response to determining that the most compressed string was obtained by application of the template-based compression technique, the most compressed string is compressed utilizing the non-template-based compression technique to obtain an output string and outputting the output string. In response to determining that the most compressed string was not obtained by application of the template-based compression technique, the most compressed string is output as the output string.

79. 发明授权

US08595463B2 Memory architecture with policy based data storage 失效
标题翻译：内存架构与基于策略的数据存储
公开(公告)号：US08595463B2
公开(公告)日：2013-11-26
申请号：US12882551
申请日：2010-09-15
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F12/10 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.
摘要翻译：介绍了一种用于存储器管理的计算系统和方法。存储器或I / O控制器接收写入请求，其中写入的数据2与地址相关联。提示信息可以与地址相关联，并且可以涉及诸如历史，O / S方向，数据优先级，作业优先级，作业重要性，作业类别，存储器类型，I / O发送者ID，延迟，功率，写入成本或读取成本组件。存储器控制器可以询问提示信息以确定存储关联数据的位置（例如，什么存储器类型或类别）。因此，数据被有效地存储在系统内。提示信息也可以用于跟踪写入后信息，并且可以被询问以确定是否应该发生数据迁移，并且应该向哪个新的存储器类型或类别移动数据。

80. 发明授权

US08495318B2 Memory page management in a tiered memory system 有权
标题翻译：分层内存系统中的内存页面管理
公开(公告)号：US08495318B2
公开(公告)日：2013-07-23
申请号：US12843718
申请日：2010-07-26
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译：包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。

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