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71. 发明授权

US08629067B2 Dielectric film growth with radicals produced using flexible nitrogen/hydrogen ratio 有权
标题翻译：使用柔性氮/氢比产生的自由基的介电膜生长
公开(公告)号：US08629067B2
公开(公告)日：2014-01-14
申请号：US12969877
申请日：2010-12-16
申请人： Jingmei Liang , Xiaolin Chen , Matthew L. Miller , Nitin K. Ingle , Shankar Venkataraman
发明人： Jingmei Liang , Xiaolin Chen , Matthew L. Miller , Nitin K. Ingle , Shankar Venkataraman
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , C23C16/345 , C23C16/452 , C23C16/56 , H01J37/32357 , H01L21/0217 , H01L21/02274 , H01L21/02326 , H01L21/02337
摘要： Methods of forming dielectric layers are described. The method may include the steps of mixing a silicon-containing precursor with a radical-nitrogen precursor, and depositing a dielectric layer on a substrate. The radical-nitrogen precursor is formed in a remote plasma by flowing hydrogen (H2) and nitrogen (N2) into the plasma in order to allow adjustment of the nitrogen/hydrogen ratio. The dielectric layer is initially a silicon-and-nitrogen-containing layer which may be converted to a silicon-and-oxygen-containing layer by curing and/or annealing the film in an oxygen-containing environment.
摘要翻译：描述形成电介质层的方法。该方法可以包括以下步骤：将含硅前体与自由基 - 氮前体混合，并在基底上沉积电介质层。通过使氢（H 2）和氮（N 2）流入等离子体中，在远离等离子体中形成自由基 - 氮前体，以便调整氮/氢比。电介质层最初是含硅和氮的层，其可以通过在含氧环境中固化和/或退火该膜而转化为含硅和氧的层。

72. 发明授权

US08497211B2 Integrated process modulation for PSG gapfill 失效
标题翻译：用于PSG填隙的集成过程调制
公开(公告)号：US08497211B2
公开(公告)日：2013-07-30
申请号：US13490426
申请日：2012-06-06
申请人： Young S. Lee , Anchuan Wang , Lan Chia Chan , Shankar Venkataraman
发明人： Young S. Lee , Anchuan Wang , Lan Chia Chan , Shankar Venkataraman
IPC分类号： H01L21/311
CPC分类号： C23C16/56 , C23C16/045 , C23C16/401 , H01L21/02129 , H01L21/02274 , H01L21/0234 , H01L21/76224
摘要： A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.
摘要翻译：在设置在衬底处理室中的衬底上沉积磷硅玻璃（PSG）膜的方法包括使用高密度等离子体工艺在衬底上沉积第一部分PSG膜。此后，PSG膜的第一部分的一部分可被回蚀刻。回蚀工艺可以包括将卤素前体流动到衬底处理室，从卤素前体形成高密度等离子体，并且在回蚀刻之后使卤素前体终止流动。该方法还包括使卤素清除剂流到衬底处理室以与衬底处理室中的残留卤素反应，并将PSG膜的第一部分暴露于含磷气体，以在整个第一部分中提供基本均匀的磷浓度的PSG电影。

73. 发明申请

US20130048605A1 DOUBLE PATTERNING ETCHING PROCESS 有权
标题翻译：双重图案蚀刻过程
公开(公告)号：US20130048605A1
公开(公告)日：2013-02-28
申请号：US13593412
申请日：2012-08-23
申请人： Kedar SAPRE , Jing Tang , Ajay Bhatnagar , Nitin Ingle , Shankar Venkataraman
发明人： Kedar SAPRE , Jing Tang , Ajay Bhatnagar , Nitin Ingle , Shankar Venkataraman
IPC分类号： B44C1/22
CPC分类号： H01L21/31144 , H01J37/32357 , H01J2237/334 , H01L21/0274 , H01L21/0337 , H01L21/3086 , H01L21/31116
摘要： A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.
摘要翻译：蚀刻衬底的方法包括在衬底上形成由氧化硅，氮化硅或氮氧化硅组成的多个双重构图特征。具有双重图案化特征的基板被提供到处理区域。包括三氟化氮，氨和氢的蚀刻气体在远程室中通电。通电的蚀刻气体被引入到工艺区中以蚀刻双重图案化特征以在衬底上形成固体残余物。固体残余物通过将基底加热至至少约100℃的温度升华。

74. 发明申请

US20130044803A1 INSTANTANEOUS DECODER REFRESH FRAME ALIGNED MULTI-BITRATE TRANSCODER OUTPUT 有权
标题翻译：瞬态解码器刷新帧对齐多位转换器输出
公开(公告)号：US20130044803A1
公开(公告)日：2013-02-21
申请号：US13209490
申请日：2011-08-15
申请人： Yuval Fisher , Hain-Ching Liu , Dan R. Hunt , Shankar Venkataraman , Hsiang-Yun Alex Huang
发明人： Yuval Fisher , Hain-Ching Liu , Dan R. Hunt , Shankar Venkataraman , Hsiang-Yun Alex Huang
IPC分类号： H04N7/40 , G06F15/16
CPC分类号： H04N21/2343 , H04N21/2402 , H04N21/242 , H04N21/6125 , H04N21/8455 , H04N21/8456
摘要： A video stream is transcoded to provide a plurality of primary profiles. Individual frames of the video stream have a Presentation Time Stamp (PTS). A PTS is used as a token to identify particular frames to be encoded as Instantaneous Decoder Refresh (IDR) frames in each profile. An IDR frame period is determined, indicative of a desired number of video frames between two IDR frames. An IDR frame is inserted into each profile every IDR frame period. The IDR frames of each profile are aligned with the same IDR frames of the other profiles. The PTS of each IDR frame in each profile is monitored. Upon determining that a PTS is out of alignment, the next PTS of the affected profile is aligned with the corresponding PTS of remaining profiles. Backup transcoders produce backup profiles that are maintained in alignment with each other and with the primary profiles.
摘要翻译：视频流被转码以提供多个主要简档。视频流的各个帧具有呈现时间戳（PTS）。使用PTS作为令牌来识别要编码为每个配置文件中的瞬时解码器刷新（IDR）帧的特定帧。确定IDR帧周期，表示两个IDR帧之间的期望数量的视频帧。每个IDR帧周期将IDR帧插入每个配置文件。每个配置文件的IDR帧与其他配置文件的相同IDR帧对齐。监视每个配置文件中每个IDR帧的PTS。在确定PTS不对齐时，受影响配置文件的下一个PTS与剩余配置文件的相应PTS对齐。备份代码转换器产生保持彼此对齐和与主配置文件对齐的备份配置文件。

75. 发明申请

US20120180954A1 SEMICONDUCTOR PROCESSING SYSTEM AND METHODS USING CAPACITIVELY COUPLED PLASMA 审中-公开
标题翻译：半导体处理系统和使用电容耦合等离子体的方法
公开(公告)号：US20120180954A1
公开(公告)日：2012-07-19
申请号：US13251663
申请日：2011-10-03
申请人： Jang-Gyoo Yang , Matthew L. Miller , Xinglong Chen , Kien N. Chuc , Qiwei Liang , Shankar Venkataraman , Dmitry Lubomirsky
发明人： Jang-Gyoo Yang , Matthew L. Miller , Xinglong Chen , Kien N. Chuc , Qiwei Liang , Shankar Venkataraman , Dmitry Lubomirsky
IPC分类号： C23F1/02 , C23C16/458 , C23C16/455 , C23C16/50
CPC分类号： H05H1/24 , C23C16/45565 , C23C16/45585 , H01J37/32091 , H01J37/32357 , H01J37/32422 , H01J37/3244 , H01J37/32449 , H01J37/32532 , H01J37/32541 , H01J37/32568 , H01J37/32724 , H01L21/02274
摘要： Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
摘要翻译：描述了具有位于处理室内的电容耦合等离子体（CCP）单元的衬底处理系统。 CCP单元可以包括形成在第一电极和第二电极之间的等离子体激发区域。第一电极可以包括允许第一气体进入等离子体激发区域的第一多个开口，并且第二电极可以包括允许活化气体离开等离子体激发区域的第二多个开口。该系统还可以包括用于将第一气体供应到CCP单元的第一电极的气体入口和可操作以支撑衬底的基座。基座位于气体反应区域的下方，活性气体从CCP单元行进。

76. 发明授权

US08114761B2 Method for doping non-planar transistors 失效
标题翻译：掺杂非平面晶体管的方法
公开(公告)号：US08114761B2
公开(公告)日：2012-02-14
申请号：US12843726
申请日：2010-07-26
申请人： Tushar V. Mandrekar , Shankar Venkataraman , Zhong Qiang Hua , Manuel A. Hernandez
发明人： Tushar V. Mandrekar , Shankar Venkataraman , Zhong Qiang Hua , Manuel A. Hernandez
IPC分类号： H01L21/00
CPC分类号： H01L21/2256 , H01L29/66803
摘要： Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.
摘要翻译：公开了通过在非平面结构上形成共形掺杂的硅玻璃层来掺杂非平面结构的方法。将其上形成有非平面结构的基板放置在化学气相沉积处理室中以沉积掺杂玻璃（例如BSG或PSG）的共形SACVD层。然后将衬底暴露于RTP或激光退火步骤以将掺杂剂扩散到非平面结构中，然后通过蚀刻去除掺杂的玻璃层。

77. 发明申请

US20120009796A1 POST-ASH SIDEWALL HEALING 审中-公开
标题翻译：后腰围护理
公开(公告)号：US20120009796A1
公开(公告)日：2012-01-12
申请号：US12909167
申请日：2010-10-21
申请人： Zhenjiang Cui , Anchuan Wang , Mehul Naik , Nitin Ingle , Young Lee , Shankar Venkataraman
发明人： Zhenjiang Cui , Anchuan Wang , Mehul Naik , Nitin Ingle , Young Lee , Shankar Venkataraman
IPC分类号： H01L21/3065
CPC分类号： H01L21/3105 , H01L21/31116 , H01L21/31138 , H01L21/76814
摘要： Methods of decreasing the effective dielectric constant present between two conducting components of an integrated circuit are described. The methods involve the use of a gas phase etch which is selective towards the oxygen-rich portion of the low-K dielectric layer. The etch rate attenuates as the etch process passes through the relatively high-K oxygen-rich portion and reaches the low-K portion. The etch process may be easily timed since the gas phase etch process does not readily remove the desirable low-K portion.
摘要翻译：描述了降低集成电路的两个导电部件之间存在的有效介电常数的方法。该方法包括使用对低K电介质层的富氧部分具有选择性的气相蚀刻。当蚀刻工艺通过较高K富氧部分并达到低K部分时，蚀刻速率衰减。由于气相蚀刻工艺不容易除去所需的低K部分，所以蚀刻工艺可以容易地定时。

78. 发明授权

US07935643B2 Stress management for tensile films 有权
标题翻译：拉伸薄膜的应力管理
公开(公告)号：US07935643B2
公开(公告)日：2011-05-03
申请号：US12604332
申请日：2009-10-22
申请人： Jingmei Liang , Anjana M. Patel , Nitin K. Ingle , Shankar Venkataraman
发明人： Jingmei Liang , Anjana M. Patel , Nitin K. Ingle , Shankar Venkataraman
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31608 , C23C16/401 , C23C16/452 , C23C16/56 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/02304 , H01L21/02326 , H01L21/02362 , H01L21/3185 , H01L21/76829 , H01L21/76834 , H01L21/76837
摘要： The formation of a gap-filling silicon oxide layer with reduced tendency towards cracking is described. The deposition involves the formation of a flowable silicon-containing layer which facilitates the filling of trenches. Subsequent processing at high substrate temperature causes less cracking in the dielectric film than flowable films formed in accordance with methods in the prior art. A compressive liner layer deposited prior to the formation of the gap-filling silicon oxide layer is described and reduces the tendency for the subsequently deposited film to crack. A compressive capping layer deposited after a flowable silicon-containing layer has also been determined to reduce cracking. Compressive liner layers and compressive capping layers can be used alone or in combination to reduce and often eliminate cracking. Compressive capping layers in disclosed embodiments have additionally been determined to enable an underlying layer of silicon nitride to be transformed into a silicon oxide layer.
摘要翻译：描述了具有降低的开裂倾向的间隙填充氧化硅层的形成。沉积涉及形成有助于填充沟槽的可流动的含硅层。在基板温度高的情况下，与根据现有技术中的方法形成的可流动膜相比，电介质膜中的裂纹少。描述在形成间隙填充氧化硅层之前沉积的压缩衬垫层，并且降低随后沉积的膜破裂的倾向。在可流动的含硅层之后沉积的压缩覆盖层也被确定以减少开裂。压缩衬里层和压缩覆盖层可以单独使用或组合使用以减少并经常消除开裂。已经确定了所公开的实施例中的压缩覆盖层，以使氮化硅的下层能够转变成氧化硅层。

79. 发明申请

US20110081782A1 POST-PLANARIZATION DENSIFICATION 失效
公开(公告)号：US20110081782A1
公开(公告)日：2011-04-07
申请号：US12787791
申请日：2010-05-26
申请人： Jingmei Liang , Nitin K. Ingle , Shankar Venkataraman
发明人： Jingmei Liang , Nitin K. Ingle , Shankar Venkataraman
IPC分类号： H01L21/3105
CPC分类号： H01L21/3105 , C23C16/345 , C23C16/452 , C23C16/56 , H01L21/02164 , H01L21/02337 , H01L21/31055 , H01L21/316 , H01L21/67207 , H01L21/76229
摘要： Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

80. 发明授权

US07902080B2 Deposition-plasma cure cycle process to enhance film quality of silicon dioxide 有权
标题翻译：沉积 - 等离子体固化循环过程，以提高二氧化硅的膜质量
公开(公告)号：US07902080B2
公开(公告)日：2011-03-08
申请号：US11753968
申请日：2007-05-25
申请人： Xiaolin Chen , Srinivas D. Nemani , Shankar Venkataraman
发明人： Xiaolin Chen , Srinivas D. Nemani , Shankar Venkataraman
IPC分类号： H01L21/302
CPC分类号： C23C16/045 , C23C16/402 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/3105 , H01L21/31633
摘要： Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the second layer. The silicon oxide layers are annealed after the gap is filled.
摘要翻译：描述了用氧化硅填充衬底上的间隙的方法。所述方法可以包括以下步骤：将有机硅前体和氧前体引入沉积室，使前体反应以在衬底上的间隙中形成第一氧化硅层，并蚀刻第一氧化硅层以还原碳内容在图层中。所述方法还可以包括在第一层上形成第二氧化硅层，并蚀刻第二层以降低第二层中的碳含量。在填充间隙之后对氧化硅层进行退火。

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