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    • 71. 发明授权
    • Thin film transistor, and display device having the thin film transistor
    • 薄膜晶体管和具有薄膜晶体管的显示装置
    • US08304779B2
    • 2012-11-06
    • US12258569
    • 2008-10-27
    • Shunpei YamazakiYasuhiro Jinbo
    • Shunpei YamazakiYasuhiro Jinbo
    • H01L29/76
    • H01L29/4908H01L29/04H01L29/66765H01L29/78609H01L29/78678H01L29/78696
    • The thin film transistor includes a gate insulating film formed over a gate electrode; a microcrystalline semiconductor film including an impurity element which serves as a donor, formed over the gate insulating film; a pair of buffer layers formed over the microcrystalline semiconductor film; a pair of semiconductor films to which an impurity element imparting one conductivity type is added, formed over the pair of buffer layers; and wirings formed over the pair of semiconductor films to which an impurity element imparting one conductivity type is added. The concentration of the impurity element which serves as a donor in the microcrystalline semiconductor film is decreased from the gate insulating film side toward the buffer layers, and the buffer layers do not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS.
    • 薄膜晶体管包括形成在栅电极上的栅极绝缘膜; 包括形成在所述栅极绝缘膜上的用作供体的杂质元素的微晶半导体膜; 形成在所述微晶半导体膜上的一对缓冲层; 在一对缓冲层上形成一对添加有赋予一种导电类型的杂质元素的半导体膜; 并且在添加有赋予一种导电类型的杂质元素的一对半导体膜上形成的布线。 作为微晶半导体膜中的供体的杂质元素的浓度从栅极绝缘膜侧朝向缓冲层减少,缓冲层不包含作为供体的杂质元素,其浓度高于 SIMS检测限。
    • 73. 发明授权
    • Thin film transistor
    • 薄膜晶体管
    • US08049215B2
    • 2011-11-01
    • US12426983
    • 2009-04-21
    • Yasuhiro JinboTomokazu Yokoi
    • Yasuhiro JinboTomokazu Yokoi
    • H01L29/786
    • H01L29/78696H01J37/32018H01J37/32091H01L29/78669H01L29/78678
    • A thin film transistor has a gate electrode; a gate insulating layer provided so as to cover the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions which is provided so that at least part of each of them overlaps the gate electrode layer and which are provided with a space therebetween; a microcrystalline semiconductor layer provided over the gate insulating layer in part of a channel length; a semiconductor layer provided over the gate insulating layer so as to cover at least the microcrystalline semiconductor layer; and an amorphous semiconductor layer provided between the semiconductor layer and the pair of impurity semiconductor layers. An impurity element which reduces the coordination number of silicon and generates dangling bonds is made to exist in the semiconductor layer.
    • 薄膜晶体管具有栅电极; 设置为覆盖所述栅极电极层的栅极绝缘层; 形成源区和漏区的一对杂质半导体层,其被设置为使得它们的至少一部分与栅电极层重叠并且在它们之间设置有空间; 在沟道长度的一部分上设置在所述栅绝缘层上的微晶半导体层; 半导体层,设置在所述栅极绝缘层上以至少覆盖所述微晶半导体层; 以及设置在所述半导体层和所述一对杂质半导体层之间的非晶半导体层。 在半导体层中存在减少硅的配位数并产生悬挂键的杂质元素。