专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07560382B2 Embedded interconnects, and methods for forming same 有权
标题翻译：嵌入式互连及其形成方法
公开(公告)号：US07560382B2
公开(公告)日：2009-07-14
申请号：US11467712
申请日：2006-08-28
申请人： Haining Yang , Thomas W. Dyer
发明人： Haining Yang , Thomas W. Dyer
IPC分类号： H01L21/44
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.
摘要翻译：本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构并且将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

72. 发明授权

US07531384B2 Enhanced interconnect structure 失效
标题翻译：增强的互连结构
公开(公告)号：US07531384B2
公开(公告)日：2009-05-12
申请号：US11548298
申请日：2006-10-11
申请人： Chih-Chao Yang , Mukta Ghate Farooq , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Mukta Ghate Farooq , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76843 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.
摘要翻译：本发明提供了一种在封盖层/电介质层/扩散阻挡界面处具有改进的机械强度的半导体互连结构。互连结构具有嵌入Cu封盖材料中的Cu扩散阻挡材料。阻挡层可以部分地嵌入盖层中或完全嵌入封盖层中。

73. 发明申请

US20080290519A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
公开(公告)号：US20080290519A1
公开(公告)日：2008-11-27
申请号：US12186932
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

74. 发明申请

US20080185662A1 STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：在场效应晶体管中形成非对称叠加电容的结构与方法
公开(公告)号：US20080185662A1
公开(公告)日：2008-08-07
申请号：US12062068
申请日：2008-04-03
申请人： Haining Yang
发明人： Haining Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823468 , H01L29/6656 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.
摘要翻译：用于形成用于半导体器件的非对称间隔结构的方法包括在设置在半导体衬底上的至少一对相邻间隔开的栅极结构上形成间隔层。栅极结构间隔开，使得间隔层在栅极结构之间的区域中以第一厚度形成，并且在其它位置处形成第二厚度，第二厚度大于所述第一厚度。蚀刻间隔层以便形成用于一对相邻隔开的栅极结构的非对称间隔结构。

75. 发明申请

US20080164558A1 METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURES USING DIBLOCK COPOLYMER PATTERNING 失效
标题翻译：使用二嵌段共聚物图案制作浅层分离结构的方法
公开(公告)号：US20080164558A1
公开(公告)日：2008-07-10
申请号：US11621124
申请日：2007-01-09
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L23/00 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/3086
摘要： A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.
摘要翻译：提供了一种隔离形成在具有绝缘体上硅（SOI）层的半导体衬底上的半导体器件的方法。该方法包括在沉积在SOI层的表面上的衬垫氮化物层上形成至少一个浅沟槽区，其中至少一个浅沟槽区包括用于暴露SOI层的一部分的开口; 在所述衬垫氮化物层和所述至少一个浅沟槽区域上施加二嵌段共聚物材料; 退火所应用的共聚物材料以形成自组织图案; 并使用二嵌段共聚物材料作为蚀刻掩模部分蚀刻浅沟槽区域。还描述了半导体结构，其具有形成在半导体衬底的SOI层上的隔离结构，该隔离结构具有氧化的衬底区域; 以及形成在氧化的基板区域上的空隙区域。

76. 发明申请

US20080142896A1 SELECTIVE STRESS ENGINEERING FOR SRAM STABILITY IMPROVEMENT 失效
标题翻译：用于SRAM稳定性改进的选择性应力工程
公开(公告)号：US20080142896A1
公开(公告)日：2008-06-19
申请号：US11612643
申请日：2006-12-19
申请人： Xiangdong Chen , Young G. Ko , Haining Yang
发明人： Xiangdong Chen , Young G. Ko , Haining Yang
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L29/7847 , Y10S257/903
摘要： An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.
摘要翻译：提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

77. 发明授权

US07388267B1 Selective stress engineering for SRAM stability improvement 失效
标题翻译： SRAM稳定性改进的选择性应力工程
公开(公告)号：US07388267B1
公开(公告)日：2008-06-17
申请号：US11612643
申请日：2006-12-19
申请人： Xiangdong Chen , Young G. Ko , Haining Yang
发明人： Xiangdong Chen , Young G. Ko , Haining Yang
IPC分类号： H01L29/78
CPC分类号： H01L27/11 , H01L29/7847 , Y10S257/903
摘要： An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.
摘要翻译：提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

78. 发明申请

US20080083991A1 SUB-LITHOGRAPHIC LOCAL INTERCONNECTS, AND METHODS FOR FORMING SAME 失效
标题翻译：次平面局部互连及其形成方法
公开(公告)号：US20080083991A1
公开(公告)日：2008-04-10
申请号：US11538550
申请日：2006-10-04
申请人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
发明人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
IPC分类号： H01L23/52
CPC分类号： H01L21/76895 , B82Y10/00 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L23/485 , H01L27/11 , H01L27/1104
摘要： The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.
摘要翻译：本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接其间没有任何金属接触。可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

79. 发明申请

US20080054313A1 DEVICE STRUCTURES INCLUDING BACKSIDE CONTACTS, AND METHODS FOR FORMING SAME 有权
标题翻译：包括背面接触的装置结构及其形成方法
公开(公告)号：US20080054313A1
公开(公告)日：2008-03-06
申请号：US11468068
申请日：2006-08-29
申请人： Thomas W. Dyer , Haining Yang
发明人： Thomas W. Dyer , Haining Yang
IPC分类号： H01L29/80
CPC分类号： H01L21/76898 , G03F9/7084 , H01L23/544 , H01L24/02 , H01L2223/54453 , H01L2924/01074 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.
摘要翻译：本发明涉及具有从衬底的背表面延伸穿过衬底到背面半导体器件的背面接触的器件结构。基板优选地还包括位于其中的一个或多个对准结构，其中每个在基板的背面处足够可见。以这种方式，可以使用这种对准结构来进行背面光刻对准，以在衬底的背面上形成图案化抗蚀剂层中的至少一个后接触开口。形成的后接触开口与前半导体器件光刻对准，并且可以被蚀刻以形成从衬底的背面延伸到前半导体器件上的后接触。用导电材料填充背面接触孔导致与前半导体器件电接触的导电背接触。

80. 发明申请

US20080036017A1 METHOD AND STRUCTURE TO USE AN ETCH RESISTANT LINER ON TRANSISTOR GATE STRUCTURE TO ACHIEVE HIGH DEVICE PERFORMANCE 审中-公开
标题翻译：在晶体闸门结构上使用耐蚀衬层以达到高设备性能的方法和结构
公开(公告)号：US20080036017A1
公开(公告)日：2008-02-14
申请号：US11836193
申请日：2007-08-09
申请人： Hung Ng , Haining Yang
发明人： Hung Ng , Haining Yang
IPC分类号： H01L31/00
CPC分类号： H01L29/665 , H01L21/823418 , H01L21/823443 , H01L21/823468 , H01L27/0629 , H01L29/6656
摘要： A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.
摘要翻译：半导体器件。该半导体器件包括：衬底，其包括：在衬底的表面上具有第一栅极堆叠的衬底，其中第一栅极堆叠具有平行于衬底的表面的顶表面和垂直于衬底表面的侧壁; 在第一栅极堆叠的侧壁上并且不在第一栅极堆叠的顶表面上的耐蚀刻的第一衬垫; 在所述第一衬垫上方的第一外隔离物，其中所述第一衬垫设置在所述第一外隔离物和所述第一栅叠层的侧壁之间，并且其中所述第一衬垫的一部分覆盖所述衬底的所述表面的第一部分; 在所述基板的表面的第二部分上的绝缘层; 以及在第一栅极堆叠的顶表面上的导电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式