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1. 发明申请

US20080197499A1 STRUCTURE FOR METAL CAP APPLICATIONS 审中-公开
标题翻译：金属盖应用结构
公开(公告)号：US20080197499A1
公开(公告)日：2008-08-21
申请号：US11675296
申请日：2007-02-15
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7684 , H01L21/76826 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

2. 发明申请

US20080111162A1 STRUCTURE AND METHOD FOR DUAL SURFACE ORIENTATIONS FOR CMOS TRANSISTORS 失效
标题翻译： CMOS晶体管双面指向的结构与方法
公开(公告)号：US20080111162A1
公开(公告)日：2008-05-15
申请号：US11559571
申请日：2006-11-14
申请人： Haining Yang , Thomas W. Dyer , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Haining Yang , Thomas W. Dyer , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/04 , H01L21/311
CPC分类号： H01L21/30608 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L21/823821 , H01L27/11 , H01L27/1104 , H01L29/7853
摘要： The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
摘要翻译：本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。或者，可以利用选择性外延生成新的面。如此形成的小面被连接以在横截面中形成λ形轮廓。新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

3. 发明申请

US20110003473A1 STRUCTURE FOR METAL CAP APPLICATIONS 有权
标题翻译：金属盖应用结构
公开(公告)号：US20110003473A1
公开(公告)日：2011-01-06
申请号：US12881806
申请日：2010-09-14
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76849
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

4. 发明授权

US07772119B2 Dual liner capping layer interconnect structure 失效
公开(公告)号：US07772119B2
公开(公告)日：2010-08-10
申请号：US12186923
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

5. 发明授权

US07709960B2 Dual liner capping layer interconnect structure 失效
标题翻译：双层衬套层互连结构
公开(公告)号：US07709960B2
公开(公告)日：2010-05-04
申请号：US12186932
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/52
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

6. 发明授权

US07531384B2 Enhanced interconnect structure 失效
标题翻译：增强的互连结构
公开(公告)号：US07531384B2
公开(公告)日：2009-05-12
申请号：US11548298
申请日：2006-10-11
申请人： Chih-Chao Yang , Mukta Ghate Farooq , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Mukta Ghate Farooq , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76843 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.
摘要翻译：本发明提供了一种在封盖层/电介质层/扩散阻挡界面处具有改进的机械强度的半导体互连结构。互连结构具有嵌入Cu封盖材料中的Cu扩散阻挡材料。阻挡层可以部分地嵌入盖层中或完全嵌入封盖层中。

7. 发明申请

US20080290519A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
公开(公告)号：US20080290519A1
公开(公告)日：2008-11-27
申请号：US12186932
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

8. 发明授权

US08133810B2 Structure for metal cap applications 有权
标题翻译：金属盖应用结构
公开(公告)号：US08133810B2
公开(公告)日：2012-03-13
申请号：US12881806
申请日：2010-09-14
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76849
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

9. 发明授权

US07544608B2 Porous and dense hybrid interconnect structure and method of manufacture 失效
标题翻译：多孔密集混合互连结构及制造方法
公开(公告)号：US07544608B2
公开(公告)日：2009-06-09
申请号：US11458464
申请日：2006-07-19
申请人： Chih-Chao Yang , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.
摘要翻译：一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

10. 发明申请

US20080293257A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
标题翻译：双层封装层互连结构
公开(公告)号：US20080293257A1
公开(公告)日：2008-11-27
申请号：US12186923
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

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