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71. 发明申请

US20070015365A1 Method and apparatus for enhanced CMP planarization using surrounded dummy design 有权
公开(公告)号：US20070015365A1
公开(公告)日：2007-01-18
申请号：US11181433
申请日：2005-07-14
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/31053
摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

72. 发明授权

US06930038B2 Dual damascene partial gap fill polymer fabrication process 失效
公开(公告)号：US06930038B2
公开(公告)日：2005-08-16
申请号：US09863647
申请日：2001-05-23
申请人： Chingfu Lin , Hsueh-Chung Chen
发明人： Chingfu Lin , Hsueh-Chung Chen
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808
摘要： A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer. The photoresist layer and the partial fill polymer layer are then removed, to expose a part of the conductive layer. The via hole and trench are filled with metal material, to form a plug and line simultaneously.

73. 发明授权

US06660627B2 Method for planarization of wafers with high selectivities 有权
标题翻译：具有高选择性的晶片平面化方法
公开(公告)号：US06660627B2
公开(公告)日：2003-12-09
申请号：US10063133
申请日：2002-03-25
申请人： Shao-Chung Hu , Hsueh-Chung Chen , Shih-Hsun Hsu , Chia-Lin Hsu
发明人： Shao-Chung Hu , Hsueh-Chung Chen , Shih-Hsun Hsu , Chia-Lin Hsu
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/31051
摘要： A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.
摘要翻译：描述了一种以高选择性平坦化半导体晶片的方法。半导体晶片具有硬掩模，设置在硬掩模上的阻挡层和设置在阻挡层上的阻挡层。该方法包括在阻挡层上进行化学机械抛光（CMP）处理，以露出停止层，并除去停止层。阻挡层相对于停止层的抛光选择性大于50.由于阻挡层的材料与阻挡层的材料不同，因此容易实现高选择性。因此，半导体晶片的表面可以被高度平坦化。

74. 发明授权

US06309555B1 Method for determining thickness of material layer and chemical mechanical polishing endpoint 失效
标题翻译：确定材料层厚度和化学机械抛光终点的方法
公开(公告)号：US06309555B1
公开(公告)日：2001-10-30
申请号：US09260202
申请日：1999-03-01
申请人： Hsueh-Chung Chen
发明人： Hsueh-Chung Chen
IPC分类号： B44C122
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12 , G01B11/0683 , G01N17/00 , H01L21/31053
摘要： A method for real-time detecting the thickness of a material layer. A reflected light is measured of an incident light emitted toward the material layer. By integrating the intensity of the reflected light along the time axis, followed by dividing by the product of the derivative of the intensity of the reflected light and the polishing time, an I-Dt transformation curve can be obtained. Since the I-Dt transformation curve has characteristics associated with a cosecant function, which has salient peaks on the curve, the thickness of the material layer can be real-time determined. Furthermore, due to the facts that the transformed curve has salient peaks, the function itself reveals the sign of the slope, and the transformed curve are relatively flat between peaks, correct and stable rules can therefore be provided to determine the analytical endpoint.
摘要翻译：一种用于实时检测材料层厚度的方法。测量朝向材料层发射的入射光的反射光。通过将反射光的强度沿着时间轴积分，然后除以反射光强度的导数与抛光时间的乘积，可以得到I-Dt变换曲线。由于I-Dt变换曲线具有与曲线上具有突出峰值的辅助功能相关联的特征，因此材料层的厚度可以被实时确定。此外，由于转换曲线具有突出峰值的事实，该函数本身揭示了斜率的符号，并且变换曲线在峰之间相对平坦，因此可以提供正确和稳定的规则来确定分析端点。

75. 发明授权

US06303461B1 Method for fabricating a shallow trench isolation structure 失效
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US06303461B1
公开(公告)日：2001-10-16
申请号：US09221203
申请日：1998-12-23
申请人： Hsueh-Chung Chen , Chien-Hung Chen
发明人： Hsueh-Chung Chen , Chien-Hung Chen
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method for fabricating a shallow trench isolation (STI) structure is provided. The method contain sequentially forming a pad oxide layer, a hard layer, and a polysilicon layer on the substrate, all of which are patterned to form a trench in the substrate to define several active areas. The hard layer usually includes silicon nitride. An insulating layer is formed over the substrate so that the trench is also filled. A CMP process is performed to polish the insulating layer. The CMP process is continuously performed until the hard layer is completely exposed. The hard layer and the pad oxide layer are sequentially removed to form the STI structure.
摘要翻译：提供了一种制造浅沟槽隔离（STI）结构的方法。该方法包括在衬底上顺序地形成衬垫氧化物层，硬质层和多晶硅层，所有这些都被图案化以在衬底中形成沟槽以限定若干有效区域。硬层通常包括氮化硅。在衬底上形成绝缘层，使得沟槽也被填充。执行CMP工艺以抛光绝缘层。连续进行CMP工艺，直到硬质层完全暴露。顺序地除去硬质层和焊盘氧化物层以形成STI结构。

76. 发明授权

US6048794A Selective W CVD plug process with a RTA self-aligned W-silicide barrier layer 失效
标题翻译：具有RTA自对准W硅化物阻挡层的选择性W CVD插塞工艺
公开(公告)号：US6048794A
公开(公告)日：2000-04-11
申请号：US954048
申请日：1997-10-20
申请人： Hsueh-Chung Chen , Chine-Gie Lou
发明人： Hsueh-Chung Chen , Chine-Gie Lou
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/76879
摘要： The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.
摘要翻译：本发明提供一种使用具有自对准的W-硅化物阻挡层34的选择性W CVD工艺制造与衬底接触的钨（W）插头36的方法。该方法包括以下步骤：将第一绝缘层20形成在硅半导体衬底10; 在第一绝缘层20中形成暴露基板表面的第一（接触）开口24; 在暴露的衬底表面上选择性地生长薄的第一钨层30; 从薄的第一钨层30快速热退火形成薄的第一硅化钨层34; 在基本上填充第一开口36的第一薄钨硅酸盐层34上选择性地沉积钨塞36，从而形成W插头接触。 RTA / W硅化物层34降低了接触电阻，增加了粘附性，并且有助于W插塞36的选择性沉积。

77. 发明授权

US6024628A Method of determining real time removal rate for polishing 失效
标题翻译：确定抛光实时清除率的方法
公开(公告)号：US6024628A
公开(公告)日：2000-02-15
申请号：US235690
申请日：1999-01-22
申请人： Hsueh-Chung Chen
发明人： Hsueh-Chung Chen
IPC分类号： B24B37/04 , B24B49/04 , B24B49/12 , B24B49/00 , B24B51/00
CPC分类号： B24B37/005 , B24B37/042 , B24B49/04 , B24B49/12
摘要： A method of determining a real time removal rate. A material layer is polished. During the polishing process, a light is incident onto the material layer continuously. The incident light is reflected from the material layer with a reflected light intensity. By integrating the reflected light intensity, followed by dividing the integration with a product of a differential of the reflected light intensity and the polishing time, an I-Dt transformation is obtained. The I-Dt transformation has a period which reflects the removal rate through calculation of optical principle.
摘要翻译：一种确定实时清除率的方法。材料层被抛光。在抛光过程中，光线连续地入射到材料层上。入射光以反射光强度从材料层反射。通过积分反射光强度，然后将积分与反射光强度和抛光时间的微分积积分，得到I-Dt变换。 I-Dt变换具有通过计算光学原理反映去除率的时间段。

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