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71. 发明授权

US5787006A Apparatus and method for management of integrated circuit layout verification processes 失效
公开(公告)号：US5787006A
公开(公告)日：1998-07-28
申请号：US640105
申请日：1996-04-30
申请人： Christophe J. Chevallier , Yarema A. Hryciw
发明人： Christophe J. Chevallier , Yarema A. Hryciw
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An apparatus and method for managing data obtained during the Design Rule Check (DRC) and Layout versus Schematic (LVS) verification procedures executed during the design of an integrated circuit. The apparatus is a data processing system which includes a database containing information regarding the schematics and layouts of the cells of an integrated circuit. The system accesses the database upon the completion of a DRC or LVS operation and queries the user as to whether the cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria.

72. 发明授权

US5694366A OP amp circuit with variable resistance and memory system including same 失效
标题翻译：具有可变电阻的OP放大电路和包括其的存储系统
公开(公告)号：US5694366A
公开(公告)日：1997-12-02
申请号：US640456
申请日：1996-05-01
申请人： Christophe J. Chevallier , Michael S. Briner
发明人： Christophe J. Chevallier , Michael S. Briner
IPC分类号： G11C5/14 , G11C16/28 , G11C16/30 , H03G1/00 , H03G3/00 , G11C7/02 , H03G3/12
CPC分类号： H03G3/001 , G11C16/28 , G11C16/30 , G11C5/143 , H03G1/0088
摘要： An operational amplifier-based voltage multiplier circuit ("op amp circuit") implemented as an integrated circuit, and a memory chip including such an op amp circuit. The op amp circuit includes a variable operational feedback or input resistance (or a variable operational feedback resistance and a variable input resistance), and preferably also circuitry for controlling at least one variable resistance in response to control bits to cause the op amp circuit to assert a selected output voltage in response to a given input voltage. Preferably, each set of control bits determines a binary control word whose binary value has a simple functional relation to the value of the output voltage selected thereby. Preferably, the memory chip includes an array of memory cells (e.g, flash memory cells) and a control unit for controlling memory operations including programming, reading, and erasing the memory cells. The op amp circuit outputs each selected output voltage in response to a different binary control word asserted by the control unit. Each binary control word is preferably determined by a set of control bits whose binary value has a simple functional relation to the value of the output voltage selected thereby. The memory chip preferably includes non-volatile data storage units which store bits of the binary control words.
摘要翻译：实现为集成电路的基于运算放大器的电压倍增器电路（“运放电路”）以及包括这种运算放大器电路的存储器芯片。运算放大器电路包括可变运行反馈或输入电阻（或可变运行反馈电阻和可变输入电阻），并且优选地还包括用于响应于控制位来控制至少一个可变电阻以使运算放大器电路断言的电路响应给定输入电压的选择的输出电压。优选地，每组控制位确定二进制控制字，其二进制值与由此选择的输出电压的值具有简单的功能关系。优选地，存储器芯片包括存储器单元阵列（例如闪存单元）和用于控制存储器操作的控制单元，包括编程，读取和擦除存储器单元。运算放大器电路响应于由控制单元确定的不同的二进制控制字输出每个选择的输出电压。每个二进制控制字优选由一组控制位确定，其二进制值与由此选择的输出电压的值具有简单的功能关系。存储器芯片优选地包括存储二进制控制字的位的非易失性数据存储单元。

73. 发明授权

US5650963A Method and apparatus for monitoring illegal conditions in a nonvolatile memory circuit 失效
标题翻译：用于监视非易失性存储器电路中的非法条件的方法和装置
公开(公告)号：US5650963A
公开(公告)日：1997-07-22
申请号：US671717
申请日：1996-06-28
申请人： Frankie F. Roohoarvar , Christophe J. Chevallier
发明人： Frankie F. Roohoarvar , Christophe J. Chevallier
IPC分类号： G11C7/24 , G11C16/22 , G11C7/00
CPC分类号： G11C16/225 , G11C7/24
摘要： A memory chip and method for operating a memory chip, in which one or more nodes are monitored to identify an illegal condition, and a halt signal is asserted in response to the illegal condition. If an illegal condition is identified during a high voltage mode in which high voltage is applied across transistors of the chip, assertion of the halt signal is delayed until the end of the high voltage mode. In response to the halt signal, the chip halts an operation such as a memory cell erase operation. By avoiding halt signal assertion during a high voltage mode, the invention avoids problems (e.g., due to the snap back bipolar effect) which could otherwise result due to switching of transistors of the chip during the process of halting chip operation in the high voltage mode. Preferably, each memory cell of the chip is a nonvolatile memory cell such as a flash memory cell, and the chip includes simple logic circuitry including a flip-flop for generating the halt signal in response to a first signal which indicates that an illegal condition has occurred and a second signal which indicates that the chip is in a low voltage mode. After being reset, the flip-flop remains in a first state for as long as the first signal indicates no illegal condition, and enters a second state in response to the first signal indicating an illegal condition. The flip-flop remains in the second state until being reset. The logic circuit outputs the halt signal only when the flip-flop is in the second state and the second signal indicates that the chip is in a low voltage mode.
摘要翻译：一种用于操作存储器芯片的存储器芯片和方法，其中监视一个或多个节点以识别非法条件，并且响应于非法条件断言停止信号。如果在芯片的晶体管上施加高电压的高电压模式下识别出非法条件，则停止信号的断言被延迟到高电压模式的结束。响应于停止信号，芯片停止诸如存储单元擦除操作的操作。通过在高电压模式期间避免停止信号断言，本发明避免了在高电压模式下停止芯片操作的过程期间由于芯片的晶体管的切换而导致的问题（例如，由于卡扣双极效应）。优选地，芯片的每个存储单元是诸如闪存单元的非易失性存储单元，并且芯片包括简单逻辑电路，其包括用于响应于指示非法状态具有的第一信号产生停止信号的触发器发生了指示芯片处于低电压模式的第二信号。在复位之后，触发器保持在第一状态，只要第一信号指示不是非法条件，并且响应于指示非法条件的第一信号而进入第二状态。触发器保持在第二状态，直到被复位。逻辑电路仅在触发器处于第二状态且第二信号指示芯片处于低电压模式时输出停止信号。

74. 发明授权

US5646429A Segmented non-volatile memory array having multiple sources 失效
标题翻译：具有多个源的分段非易失性存储器阵列
公开(公告)号：US5646429A
公开(公告)日：1997-07-08
申请号：US606245
申请日：1996-02-23
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/04 , H01L27/115 , G11C11/40 , H01L27/15
CPC分类号： H01L27/11519 , G11C16/0416 , H01L27/115
摘要： An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns. The metallic source line of one of the erase blocks extends over, but is not connected to, the adjacent erase block, with the source lines of the erase blocks preferably being connected to a common source line decoder used to control the status of a selected one of the source lines so that a selected one of the erase blocks can be erased.
摘要翻译：非易失性存储器单元的布置，诸如闪存单元，其包括可被单独擦除并且需要减少电路面积的擦除块。擦除块各自包括排列成行和列的单元阵列。一排中的每个单元的控制栅极连接到公共字线，其漏极连接到公共位线。一个擦除块的所有源通过源极线结构连接在一起，该源极线结构包括非金属源极线，例如掺杂半导体线，其通常相对于字线平行并且互连位于一排。源极线结构还包括至少一个金属源极线，其功能是互连位于擦除块单元列之一中的单元的源极区域。一个擦除块的金属源极线延伸过去但不连接到相邻的擦除块，其中擦除块的源极线优选地连接到用于控制所选择的一个的状态的公共源极线解码器的源极线，使得可以擦除所选择的一个擦除块。

75. 发明授权

US5313429A Memory circuit with pumped voltage for erase and program operations 失效
标题翻译：具有抽取电压的存储器电路用于擦除和编程操作
公开(公告)号：US5313429A
公开(公告)日：1994-05-17
申请号：US837303
申请日：1992-02-14
申请人： Christophe J. Chevallier , Asim A. Bajwa , Darrell D. Rinerson , Steve K. Hsia
发明人： Christophe J. Chevallier , Asim A. Bajwa , Darrell D. Rinerson , Steve K. Hsia
IPC分类号： G11C5/14 , G11C16/30 , G11C16/02
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.
摘要翻译：公开了一种采用热电子注入进行编程操作和Fowler-Nordheim隧道进行擦除操作的存储器件。存储器件只需要一个5伏电源，不需要外部高电压电源进行编程或擦除操作。存储器件包括电荷泵部分，其在内部产生编程和擦除操作所需的高电压。同样的电荷泵部分用于编程和擦除电源要求。

76. 发明授权

US5216588A Charge pump with high output current 失效
标题翻译：高输出电流的电荷泵
公开(公告)号：US5216588A
公开(公告)日：1993-06-01
申请号：US837172
申请日：1992-02-14
申请人： Asim A. Bajwa , Christophe J. Chevallier
发明人： Asim A. Bajwa , Christophe J. Chevallier
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： A charge pump circuit is disclosed that enables the conversion of a low voltage to a higher voltage while delivering a substantial amount of current. The charge pump circuit includes a plurality of diode-capacitor voltage multiplier pump units connected in parallel with respect to each other. The plurality of pump units are switched at different times during the pump frequency to minimize noise generation. In one embodiment, the charge pump circuit is capable of delivering 8 mA of current.
摘要翻译：公开了一种电荷泵电路，其能够在输送大量电流的同时将低电压转换为较高电压。电荷泵电路包括相对于彼此并联连接的多个二极管 - 电容器电压倍增器泵单元。在泵频率期间，多个泵单元在不同时间被切换以最小化噪声产生。在一个实施例中，电荷泵电路能够传送8mA的电流。

77. 发明授权

US08369145B2 Apparatus and method for detecting over-programming condition in multistate memory device 失效
标题翻译：多状态存储器件中过度编程条件的检测装置及方法
公开(公告)号：US08369145B2
公开(公告)日：2013-02-05
申请号：US13410771
申请日：2012-03-02
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G11C11/34
CPC分类号： G11C29/765 , G06F11/1072 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/04 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/00 , G11C29/52 , G11C29/76 , G11C29/82 , G11C2029/0409 , G11C2211/5643
摘要： A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.
摘要翻译：系统实施例包括非易失性存储器件，存储器和控制器。非易失性存储器件包括多个非易失性存储单元。每个非易失性存储器单元适于存储至少两个位。存储器适于在系统上电时存储程序。控制器适于实现程序以提供用于编程和擦除非易失性存储器单元的指令。方法实施例包括在为存储器系统加电时将程序加载到存储器中，以及使用包括编程和擦除多位非易失性存储器单元的控制器来实现程序。

78. 发明授权

US07251187B2 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure 有权
标题翻译：可在不同模式下操作的存储器系统，方法和预解码电路，用于选择性地访问存储器单元的多个块以用于同时写入或擦除
公开(公告)号：US07251187B2
公开(公告)日：2007-07-31
申请号：US11212329
申请日：2005-08-26
申请人： Vinod C. Lakhani , Christophe J. Chevallier , Mathew L. Adsitt
发明人： Vinod C. Lakhani , Christophe J. Chevallier , Mathew L. Adsitt
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C8/12 , G11C16/08
摘要： A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.
摘要翻译：公开了一种包括非易失性闪速存储器和用于同时选择多个存储块的方法的存储器系统。存储器系统被组织成多个主块，每个主块具有多个较小的块，模拟磁盘驱动器。控制线激活多种模式。在第一模式中，高阶地址线仅选择一个块，而在第二模式中，选择用户指定的多个块。通过加载具有选择位的寄存器或直接使用某些地址线作为选择位来选择块。每个位指定一个块，每个位独立于其他位。存储器系统还包括预解码器和控制器，其控制预解码器和寄存器以便选择至少两个存储单元块。在第三模式中，选择所有块，并且在第四模式中，所有块都被取消选择。选择多个块可以同时擦除，写入和读取存储在存储器中的多个字节。

79. 发明授权

US07167396B2 Erase verify for nonvolatile memory using reference current-to-voltage converters 有权
标题翻译：使用参考电流 - 电压转换器擦除非易失性存储器的验证
公开(公告)号：US07167396B2
公开(公告)日：2007-01-23
申请号：US11198200
申请日：2005-08-05
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/34 , G11C16/28
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译：存储器件验证系统确定存储器中存储器单元的状态。存储器包括具有耦合到位线的多个存储器单元的存储器阵列。验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。验证电路可以包括第一和第二比较器。在一个实施例中，第一比较器用于将位线电流与较高的第一参考电流进行比较。第二比较器用于将位线电流与较低的第二参考电流进行比较。比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。

80. 发明授权

US07123516B2 Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters 有权
标题翻译：使用位线/参考电流 - 电压转换器擦除非易失性存储器的验证
公开(公告)号：US07123516B2
公开(公告)日：2006-10-17
申请号：US11198199
申请日：2005-08-05
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/34 , G11C16/02
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译：存储器件验证系统确定存储器中存储器单元的状态。存储器包括具有耦合到位线的多个存储器单元的存储器阵列。验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。验证电路可以包括第一和第二比较器。在一个实施例中，第一比较器用于将位线电流与较高的第一参考电流进行比较。第二比较器用于将位线电流与较低的第二参考电流进行比较。比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。

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