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1. 发明授权

US08369145B2 Apparatus and method for detecting over-programming condition in multistate memory device 失效
标题翻译：多状态存储器件中过度编程条件的检测装置及方法
公开(公告)号：US08369145B2
公开(公告)日：2013-02-05
申请号：US13410771
申请日：2012-03-02
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G11C11/34
CPC分类号： G11C29/765 , G06F11/1072 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/04 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/00 , G11C29/52 , G11C29/76 , G11C29/82 , G11C2029/0409 , G11C2211/5643
摘要： A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.
摘要翻译：系统实施例包括非易失性存储器件，存储器和控制器。非易失性存储器件包括多个非易失性存储单元。每个非易失性存储器单元适于存储至少两个位。存储器适于在系统上电时存储程序。控制器适于实现程序以提供用于编程和擦除非易失性存储器单元的指令。方法实施例包括在为存储器系统加电时将程序加载到存储器中，以及使用包括编程和擦除多位非易失性存储器单元的控制器来实现程序。

2. 发明授权

US06519691B2 Method of controlling a memory device by way of a system bus 有权
标题翻译：通过系统总线控制存储器件的方法
公开(公告)号：US06519691B2
公开(公告)日：2003-02-11
申请号：US09854343
申请日：2001-05-11
申请人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
发明人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
IPC分类号： G06F1200
CPC分类号： G06F12/0661 , G06F2212/2022
摘要： A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.
摘要翻译：具有存储器控制器，存储器单元阵列和存储器操作管理器的非易失性存储器系统。操作管理器通常通过系统总线从控制器接收到程序，读取和擦除指令后执行存储器程序，读取和擦除操作。在管理器中提供地址块电路，其能够根据由控制器确定的地址块电路的状态在单个地址或多个地址上执行存储器操作。可以基于由控制器提供的单个地址来生成多个地址，使得可以编程或读取存储器的扇区，从而简化存储器操作并减少存储器控制器的开销。

3. 发明授权

US5815458A System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers 失效
公开(公告)号：US5815458A
公开(公告)日：1998-09-29
申请号：US709555
申请日：1996-09-06
申请人： Christophe J. Chevallier , Vinod C. Lakhani , Robert D. Norman , Darrell D. Rinerson
发明人： Christophe J. Chevallier , Vinod C. Lakhani , Robert D. Norman , Darrell D. Rinerson
IPC分类号： G11C8/08 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08 , G11C8/08
摘要： A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline. In some embodiments, one set of wordline drivers (positioned along one side of the array) drives the even-numbered wordlines, another set of wordline drivers (positioned along the opposite side of the array) drives the odd-numbered wordlines, and the system exchanges the bitline addresses of the first packet and last packet (or the first N bytes of the first packet and the last N bytes of the last packet) of each sector to be written to cells along an even-numbered wordline (or inverts the bitline addresses for the entire sector), but the system does not modify the bitline address of any of data bit to be written to cells connected along an odd-numbered wordline. Preferably, the system is operable in either a first mode in which it modifies the addresses to which data is to be written to a cell array (to reduce the time needed to read the data after it has been written) or a second mode in which it does not modify the addresses to which the data is to be written to the array.

4. 发明授权

US5771346A Apparatus and method for detecting over-programming condition in multistate memory device 失效
公开(公告)号：US5771346A
公开(公告)日：1998-06-23
申请号：US736195
申请日：1996-10-24
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G06F11/10 , G11C11/56 , G11C29/00 , G11C29/52 , G11C11/34
CPC分类号： G11C29/765 , G06F11/1072 , G11C11/5621 , G11C11/5628 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/52 , G11C29/76 , G11C29/82 , G11C7/1039 , G11C16/04 , G11C2029/0409 , G11C2211/5643 , G11C29/00
摘要： An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

5. 发明授权

US07457997B2 Apparatus and method for detecting over-programming condition in multistate memory device 失效
标题翻译：多状态存储器件中过度编程条件的检测装置及方法
公开(公告)号：US07457997B2
公开(公告)日：2008-11-25
申请号：US10629279
申请日：2003-07-29
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G11C29/00 , G11C16/06 , G11C16/04 , G11C7/00
CPC分类号： G11C29/765 , G06F11/1072 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/04 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/00 , G11C29/52 , G11C29/76 , G11C29/82 , G11C2029/0409 , G11C2211/5643
摘要： An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.
摘要翻译：一种用于检测多态存储器单元中的过编程状态的装置和方法。本发明还涉及识别过程编程的单元并提供写入用于过程编程单元的数据的备用位置。当发现包含在多状态存储器单元中的数据相对于其预期编程（阈值电压电平）状态被发现过度编程时，过程编程状态检测电路产生错误信号。在检测到过度编程的单元时，修改存储器系统的编程操作以中止对单元的进一步编程尝试。过度编程状态检测电路还用于帮助校正过度编程状态，允许由存储器系统补偿编程错误。

6. 发明授权

US06320815B1 Memory system having flexible bus structure and method 有权
标题翻译：具有灵活总线结构和方法的存储系统
公开(公告)号：US06320815B1
公开(公告)日：2001-11-20
申请号：US09711623
申请日：2000-11-13
申请人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
发明人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
IPC分类号： G11C800
CPC分类号： G06F12/0661
摘要： A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.
摘要翻译：一种具有通过系统总线连接到多个存储器件的存储器控制器的存储器系统。存储器控制器通过系统总线向存储器件发出器件选择，存储器程序和存储器读取指令，器件选择指令包括器件选择地址和器件选择命令。存储器件各自包括存储器单元阵列和用于对阵列执行存储器读取和编程操作的存储器操作管理器。存储器操作管理器包括地址比较器，其将系统总线上接收的设备选择地址与存储在存储设备中的本地地址进行比较，以及命令解码器，其用于检测系统总线上的命令，存储器操作管理器操作以切换存储器设备从设备禁用状态到启用设备的状态，当存储设备接收与本地地址匹配的选择地址以及设备选择命令之一时。

7. 发明授权

US6073204A Memory system having flexible architecture and method 失效
公开(公告)号：US6073204A
公开(公告)日：2000-06-06
申请号：US839034
申请日：1997-04-23
申请人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
发明人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
IPC分类号： A22C17/00 , G06F12/06 , G06F12/00
CPC分类号： G06F12/0676
摘要： A memory system having a single memory controller connected to several memory devices by way of a common bus, with the memory controller configured to issue memory program, memory read and memory erase instructions over the system bus to a selected one of the memory devices. Each memory device has an array of memory cells and several volatile control registers which contain control parameters provided by the memory controller. The control parameters operate to control one or more of the voltages applied to the array in memory read, program and erase operations, including the timing of the application of the voltages and the magnitude of the voltages so that the memory operations can be optimized by the memory controller.

8. 发明授权

US06567335B1 Memory system having flexible bus structure and method 有权
公开(公告)号：US06567335B1
公开(公告)日：2003-05-20
申请号：US09711416
申请日：2000-11-13
申请人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
发明人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
IPC分类号： G11C700
CPC分类号： G06F12/0661
摘要： A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.

9. 发明授权

US06396729B1 Memory system having flexible bus structure and method 有权
公开(公告)号：US06396729B1
公开(公告)日：2002-05-28
申请号：US09711413
申请日：2000-11-13
申请人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
发明人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
IPC分类号： G11C700
CPC分类号： G06F12/0661
摘要： A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.

10. 发明授权

US06363454B1 Memory system having flexible architecture and method 失效
标题翻译：具有灵活架构和方法的内存系统
公开(公告)号：US06363454B1
公开(公告)日：2002-03-26
申请号：US09551650
申请日：2000-04-18
申请人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
发明人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
IPC分类号： G06F1200
CPC分类号： G06F12/0676
摘要： A memory system having a single memory controller connected to several memory devices by way of a common bus, with the memory controller configured to issue memory program, memory read and memory erase instructions over the system bus to a selected one of the memory devices. Each memory device has an array of memory cells and several volatile control registers which contain control parameters provided by the memory controller. The control parameters operate to control one or more of the voltages applied to the array in memory read, program and erase operations, including the timing of the application of the voltages and the magnitude of the voltages so that the memory operations can be optimized by the memory controller.
摘要翻译：一种具有通过公共总线连接到多个存储器件的单个存储器控制器的存储器系统，所述存储器控制器被配置为通过所述系统总线向存储器设备中选择的一个发出存储器程序，存储器读取和存储器擦除指令。每个存储器件具有存储器单元阵列和若干易失性控制寄存器，其包含由存储器控制器提供的控制参数。控制参数用于控制在存储器读取，编程和擦除操作中施加到阵列的一个或多个电压，包括施加电压的时间和电压的大小，使得存储器操作可以由内存控制器

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