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1. 发明授权

US5650963A Method and apparatus for monitoring illegal conditions in a nonvolatile memory circuit 失效
标题翻译：用于监视非易失性存储器电路中的非法条件的方法和装置
公开(公告)号：US5650963A
公开(公告)日：1997-07-22
申请号：US671717
申请日：1996-06-28
申请人： Frankie F. Roohoarvar , Christophe J. Chevallier
发明人： Frankie F. Roohoarvar , Christophe J. Chevallier
IPC分类号： G11C7/24 , G11C16/22 , G11C7/00
CPC分类号： G11C16/225 , G11C7/24
摘要： A memory chip and method for operating a memory chip, in which one or more nodes are monitored to identify an illegal condition, and a halt signal is asserted in response to the illegal condition. If an illegal condition is identified during a high voltage mode in which high voltage is applied across transistors of the chip, assertion of the halt signal is delayed until the end of the high voltage mode. In response to the halt signal, the chip halts an operation such as a memory cell erase operation. By avoiding halt signal assertion during a high voltage mode, the invention avoids problems (e.g., due to the snap back bipolar effect) which could otherwise result due to switching of transistors of the chip during the process of halting chip operation in the high voltage mode. Preferably, each memory cell of the chip is a nonvolatile memory cell such as a flash memory cell, and the chip includes simple logic circuitry including a flip-flop for generating the halt signal in response to a first signal which indicates that an illegal condition has occurred and a second signal which indicates that the chip is in a low voltage mode. After being reset, the flip-flop remains in a first state for as long as the first signal indicates no illegal condition, and enters a second state in response to the first signal indicating an illegal condition. The flip-flop remains in the second state until being reset. The logic circuit outputs the halt signal only when the flip-flop is in the second state and the second signal indicates that the chip is in a low voltage mode.
摘要翻译：一种用于操作存储器芯片的存储器芯片和方法，其中监视一个或多个节点以识别非法条件，并且响应于非法条件断言停止信号。如果在芯片的晶体管上施加高电压的高电压模式下识别出非法条件，则停止信号的断言被延迟到高电压模式的结束。响应于停止信号，芯片停止诸如存储单元擦除操作的操作。通过在高电压模式期间避免停止信号断言，本发明避免了在高电压模式下停止芯片操作的过程期间由于芯片的晶体管的切换而导致的问题（例如，由于卡扣双极效应）。优选地，芯片的每个存储单元是诸如闪存单元的非易失性存储单元，并且芯片包括简单逻辑电路，其包括用于响应于指示非法状态具有的第一信号产生停止信号的触发器发生了指示芯片处于低电压模式的第二信号。在复位之后，触发器保持在第一状态，只要第一信号指示不是非法条件，并且响应于指示非法条件的第一信号而进入第二状态。触发器保持在第二状态，直到被复位。逻辑电路仅在触发器处于第二状态且第二信号指示芯片处于低电压模式时输出停止信号。

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