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71. 发明授权

US07069459B2 Clock skew reduction technique based on distributed process monitors 有权
标题翻译：基于分布式过程监视器的时钟偏差减少技术
公开(公告)号：US07069459B2
公开(公告)日：2006-06-27
申请号：US10385414
申请日：2003-03-10
申请人： Claude R. Gauthier , Shaishav Desai
发明人： Claude R. Gauthier , Shaishav Desai
IPC分类号： G06F1/12
CPC分类号： G06F1/10
摘要： A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.
摘要翻译：用于调整时钟偏移的方法和装置涉及使用分布在该装置上的多个振荡器，其中多个振荡器中的至少一个具有取决于装置的特性的频率。处理器被布置成根据频率调整偏置发生器。偏置发生器布置成通过可调缓冲器来调节延迟。可调缓冲器被布置为根据取决于偏置发生器的可调谐缓冲器的延迟调整而传播时钟信号。

72. 发明授权

US07043683B2 Data transmission update technique in low power modes 有权
标题翻译：低功耗模式下的数据传输更新技术
公开(公告)号：US07043683B2
公开(公告)日：2006-05-09
申请号：US10360312
申请日：2003-02-07
申请人： Brian W. Amick , Claude R. Gauthier , Aninda Roy
发明人： Brian W. Amick , Claude R. Gauthier , Aninda Roy
IPC分类号： G03M13/00 , G01R31/28
CPC分类号： G06F1/3209 , H04J3/06 , H04L7/0037
摘要： A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.
摘要翻译：提供了一种用于计算机系统的低功率模式和/或低活动模式的数据传输更新技术或其一部分。当处于低功率模式和/或低活动模式时，该技术启动对数据传输的测试，其结果用于调整数据接收的时间，以便促进准确和及时的日期通信。

73. 发明授权

US07017086B2 Round-robin updating for high speed I/O parallel interfaces 有权
标题翻译：高速I / O并行接口循环更新
公开(公告)号：US07017086B2
公开(公告)日：2006-03-21
申请号：US10174045
申请日：2002-06-18
申请人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
发明人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
IPC分类号： G01R31/28
CPC分类号： G01R31/31727
摘要： A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.
摘要翻译：用于调整通信系统的技术涉及多个链路，其中每个链路包括适于传输数据信号的数据线和适于发送时钟信号的时钟线。测试电路连接到测试电路测试多个链路中的至少一个的多个链路。测试电路包括调整电路，该调整电路被布置成基于偏移量从多个链路中的一个链路的时钟信号产生可调节时钟信号，其中调整电路相对于一个数据信号调整可调节时钟信号的定时的多个链接。该测试电路适用于执行多个链路的循环测试。

74. 发明授权

US06996491B2 Method and system for monitoring and profiling an integrated circuit die temperature 有权
公开(公告)号：US06996491B2
公开(公告)日：2006-02-07
申请号：US10079476
申请日：2002-02-19
申请人： Spencer M. Gold , Claude R. Gauthier , Steven R. Boyle , Kenneth A. House , Joseph Siegel
发明人： Spencer M. Gold , Claude R. Gauthier , Steven R. Boyle , Kenneth A. House , Joseph Siegel
IPC分类号： G01K1/08
CPC分类号： G06F1/206
摘要： A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

75. 发明授权

US06914452B2 Adaptive keeper sizing for dynamic circuits based on fused process corner data 有权
标题翻译：基于融合过程角数据的动态电路的自适应保持器尺寸
公开(公告)号：US06914452B2
公开(公告)日：2005-07-05
申请号：US10246307
申请日：2002-09-17
申请人： Claude R. Gauthier , Shaishav A. Desai
发明人： Claude R. Gauthier , Shaishav A. Desai
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.
摘要翻译：本发明提供一种自适应保持电路。自适应保持器电路包括具有与电源电连通的第一端子和与内部动态节点电通信的第二端子的第一保持器晶体管。此外，包括与第一保持晶体管并联配置的第二保持晶体管。第二保持器晶体管还具有与电源电连通的第一端子。可以使用反馈位线将第二保持晶体管添加到第一保持晶体管，反馈位线被配置为基于反馈位线的状态来控制第二保持器晶体管和内部动态节点之间的电流。反馈位线的状态基于芯片的工艺角特性。可以将附加的保持器晶体管和相应的反馈位线添加到保持器电路以增加灵活性。

76. 发明授权

US06871290B2 Method for reducing a magnitude of a rate of current change of an integrated circuit 有权
标题翻译：降低集成电路电流变化率的方法
公开(公告)号：US06871290B2
公开(公告)日：2005-03-22
申请号：US09930373
申请日：2001-08-14
申请人： Claude R. Gauthier , Tyler J. Thorp , Richard L. Wheeler , Brian W. Amick
发明人： Claude R. Gauthier , Tyler J. Thorp , Richard L. Wheeler , Brian W. Amick
IPC分类号： H03K17/16 , H03K17/693 , G06F1/26 , G06F1/32
CPC分类号： H03K17/164 , H03K17/693
摘要： A method for reducing a magnitude of a rate of current change of an integrated circuit is provided. The method uses a plurality of transistors controlled by a finite state machine, such as a counter, to gradually reduce current sourced from a power supply. Further, the finite state machine is controlled by a micro-architectural stage that determines when the integrated circuit needs to be powered down.
摘要翻译：提供了一种用于减小集成电路的电流变化率的幅度的方法。该方法使用由诸如计数器的有限状态机控制的多个晶体管来逐渐减少源自电源的电流。此外，有限状态机由微架构级控制，确定集成电路何时需要掉电。

77. 发明授权

US06850856B1 I/O receiver thermal correction scheme 有权
标题翻译： I / O接收机热校正方案
公开(公告)号：US06850856B1
公开(公告)日：2005-02-01
申请号：US10299674
申请日：2002-11-18
申请人： Claude R. Gauthier , Shaishav A. Desai
发明人： Claude R. Gauthier , Shaishav A. Desai
IPC分类号： G01R19/00 , G06F1/20 , G06F1/32 , G06F19/00
CPC分类号： G06F1/32 , G06F1/206
摘要： A system and method of adjusting an I/O receiver includes providing an amplification control parameter to the I/O receiver. A temperature of the I/O receiver is monitored and the amplification control parameter to the I/O receiver is adjusted according to the temperature of the I/O receiver.
摘要翻译：调整I / O接收机的系统和方法包括向I / O接收机提供放大控制参数。监视I / O接收器的温度，并根据I / O接收器的温度调节I / O接收器的放大控制参数。

78. 发明授权

US06842351B2 Method and apparatus for I/O resonance compensation 有权
标题翻译：用于I / O谐振补偿的方法和装置
公开(公告)号：US06842351B2
公开(公告)日：2005-01-11
申请号：US10370901
申请日：2003-02-20
申请人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
发明人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
IPC分类号： H02J1/02 , H05K1/02 , H00M1/14
CPC分类号： H02J1/02 , H05K1/0216
摘要： A computer system uses a power distribution network arranged to propagate at least one voltage potential to an integrated circuit. A resonance detector is arranged to detect a power supply resonance. A damping circuit is operatively connected to the resonance detector and the power distribution network. The damping circuit resides external to the integrated circuit and dampens the power supply resonance under control of the resonance detector.
摘要翻译：计算机系统使用布置成将至少一个电压电势传播到集成电路的配电网络。谐振检测器被布置成检测电源谐振。阻尼电路可操作地连接到谐振检测器和配电网络。阻尼电路位于集成电路的外部，并在谐振检测器的控制下抑制电源谐振。

79. 发明授权

US06842057B1 Analog state recovery technique for DLL design 有权
标题翻译：用于DLL设计的模拟状态恢复技术
公开(公告)号：US06842057B1
公开(公告)日：2005-01-11
申请号：US10638805
申请日：2003-08-11
申请人： Claude R. Gauthier , Aninda K. Roy
发明人： Claude R. Gauthier , Aninda K. Roy
IPC分类号： H03L7/081 , H03L7/089 , H03L7/093 , H03L7/14 , H03L7/06
CPC分类号： H03L7/14 , H03L7/0812 , H03L7/0891 , H03L7/093
摘要： A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is arranged to carry a clock signal. The delay locked loop operatively connects to the clock path where the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop. An analog state storage apparatus operatively connects to the delay locked loop and is arranged to store the voltage potential. Also, the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal.
摘要翻译：一种方法和装置存储由延迟锁定环产生的电压电位，以便减少延迟锁定环从丢失时钟状态恢复所需的时间。时钟路径被布置成携带时钟信号。延迟锁定环路可操作地连接到时钟路径，其中延迟锁定环路被布置成产生取决于时钟信号和延迟锁定环路的延迟时钟信号输出之间的相位差的电压电位。模拟状态存储装置可操作地连接到延迟锁定环路并且被布置成存储电压电位。此外，模拟状态存储装置被布置为响应于时钟信号和延迟的时钟信号中的至少一个的丢失而将存储的电压电压输出到延迟锁定环路。

80. 发明授权

US06700390B2 Adjustment and calibration system to store resistance settings to control chip/package resonance 有权
标题翻译：调整和校准系统存储电阻设置以控制芯片/封装谐振
公开(公告)号：US06700390B2
公开(公告)日：2004-03-02
申请号：US10160349
申请日：2002-05-31
申请人： Claude R. Gauthier , Brian W. Amick
发明人： Claude R. Gauthier , Brian W. Amick
IPC分类号： G01R2700
CPC分类号： G06F1/26 , G06F1/189
摘要： A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.
摘要翻译：提供了用于降低集成电路的电源路径的阻抗的调整和校准系统。电源路径包括第一电源线和向集成电路提供电力的第二电源线。至少连接在第一电源线和第二电源线之间的数字电位器被调节以减小电源路径的阻抗。代表数字电位器的期望值的控制信息存储在存储装置中。随后选择性地读出存储在存储装置中的控制信息，以便将数字电位计调整到与控制信息相对应的状态。

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