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71. 发明申请

US20050032316A1 Cross diffusion barrier layer in polysilicon 有权
标题翻译：多晶硅中的交叉扩散阻挡层
公开(公告)号：US20050032316A1
公开(公告)日：2005-02-10
申请号：US10931377
申请日：2004-08-31
申请人： Sanh Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene Gifford
发明人： Sanh Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene Gifford
IPC分类号： H01L21/8238 , H01L21/8244 , H01L27/11 , H01L29/49 , H01L21/8234
CPC分类号： H01L27/11 , H01L21/823842 , H01L21/823871 , H01L27/1104 , H01L29/4941 , Y10S257/903 , Y10S438/927
摘要： A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.
摘要翻译：半导体器件包括夹在栅极层和电极层之间的交叉扩散阻挡层。栅极层具有与第二导电类型的掺杂多晶硅的第二栅极部分相邻的第一导电类型的掺杂多晶硅的第一栅极部分。交叉扩散阻挡层包括硅和氮的组合。交叉扩散阻挡层充分地防止了第一和第二栅极部分之间的交叉扩散，同时不会显着增加栅极层的电阻。

72. 发明申请

US20050003627A1 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20050003627A1
公开(公告)日：2005-01-06
申请号：US10901538
申请日：2004-07-28
申请人： Todd Abbott , Zhongze Wang , Jigish Trivedi , Chih-Chen Cho
发明人： Todd Abbott , Zhongze Wang , Jigish Trivedi , Chih-Chen Cho
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/417 , H01L21/84 , H01L21/00 , H01L21/76
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。源极/漏极区域形成在沟道区域的相对侧上。绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。半导体通道材料形成在空隙内。相邻的源极/漏极区域横向靠近通道材料提供。在通道材料上形成一个栅极。集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

73. 发明授权

US06812529B2 Suppression of cross diffusion and gate depletion 有权
公开(公告)号：US06812529B2
公开(公告)日：2004-11-02
申请号：US09808864
申请日：2001-03-15
申请人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
发明人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
IPC分类号： H01L2949
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

74. 发明授权

US06613617B2 Cross-diffusion resistant dual-polycide semiconductor structure and method 失效
公开(公告)号：US06613617B2
公开(公告)日：2003-09-02
申请号：US10282420
申请日：2002-10-28
申请人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
发明人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
IPC分类号： H01L2184
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

75. 发明授权

US06501114B2 Structures comprising transistor gates 有权
标题翻译：包括晶体管栅极的结构
公开(公告)号：US06501114B2
公开(公告)日：2002-12-31
申请号：US09938463
申请日：2001-08-23
申请人： Chih-Chen Cho , Richard H. Lane , Charles H. Dennison
发明人： Chih-Chen Cho , Richard H. Lane , Charles H. Dennison
IPC分类号： H01L27108
CPC分类号： H01L21/76897 , H01L21/28247 , H01L21/76829 , H01L21/823425 , H01L21/823468 , H01L27/10894
摘要： The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
摘要翻译：本发明包括形成晶体管结构的一部分的方法。提供衬底，并且在衬底上形成晶体管栅极。晶体管栅极具有侧壁。通过高密度等离子体沉积，氧化硅沉积在靠近晶体管栅极的衬底的一部分上。在氧化硅上并沿着晶体管栅极的侧壁形成间隔物。本发明还包括氧化导电结构的一部分的方法。另外，本发明涵盖晶体管栅极结构以及包括存储器阵列和外围电路的结构。

76. 发明授权

US06290808B1 Chemical mechanical polishing machine with ultrasonic vibration and method 有权
标题翻译：化学机械抛光机采用超声波振动和方法
公开(公告)号：US06290808B1
公开(公告)日：2001-09-18
申请号：US09287378
申请日：1999-04-07
申请人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho
发明人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho
IPC分类号： C23F102
CPC分类号： B24B37/30 , B24B1/04 , B24B37/042 , B24B49/14
摘要： A chemical mechanical polishing machine with ultrasonic vibration is disclosed. The chemical mechanical polishing machine (10) includes a movable abrasive surface (14). A wafer holder (12) holds a wafer (18) in contact with the abrasive surface (14), and a vibration generator (16) vibrates the wafer (18) during polishing. The ultrasonic vibration agitates the slurry and provides an additional degree of motion between the wafer and the abrasive surface, thereby increasing the speed and uniformity of the polishing.
摘要翻译：公开了一种具有超声波振动的化学机械抛光机。化学机械抛光机（10）包括可动研磨表面（14）。晶片保持器（12）保持与研磨表面（14）接触的晶片（18），并且振动发生器（16）在抛光期间振动晶片（18）。超声波振动搅拌浆料并在晶片和研磨表面之间提供额外的运动程度，从而提高抛光的速度和均匀性。

77. 发明授权

US6093642A Tungsten-nitride for contact barrier application 有权
标题翻译：用于接触屏障应用的氮化钨
公开(公告)号：US6093642A
公开(公告)日：2000-07-25
申请号：US354508
申请日：1999-07-15
申请人： Chih-Chen Cho , Yoshimitsu Tamura , Jiong-Ping Lu
发明人： Chih-Chen Cho , Yoshimitsu Tamura , Jiong-Ping Lu
IPC分类号： H01L21/768 , H01L21/28 , H01L21/285 , H01L23/485 , H01L21/4763
CPC分类号： H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： A contact and method of forming a contact. A layer of titanium (112) is deposited. Then, a RTP anneal is performed to react the titanium layer (112) with underlying silicon (112) to form a silicide layer (114). After the RTP anneal, a layer of tungsten-nitride (116) is deposited as a barrier layer. The metal interconnect layer (118) is then formed over the tungsten-nitride layer (116).
摘要翻译：形成接触的接触和方法。沉积一层钛（112）。然后，执行RTP退火以使钛层（112）与下面的硅（112）反应以形成硅化物层（114）。在RTP退火之后，沉积一层氮化钨（116）作为阻挡层。然后在氮化钨层（116）之上形成金属互连层（118）。

78. 发明授权

US5750415A Low dielectric constant layers via immiscible sol-gel processing 失效
标题翻译：低介电常数层通过不混溶溶胶 - 凝胶加工
公开(公告)号：US5750415A
公开(公告)日：1998-05-12
申请号：US250747
申请日：1994-05-27
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02362 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L21/76834 , H01L2924/0002
摘要： A method for forming air gaps 22 between metal leads 16 of a semiconductor device. A metal layer is deposited on a substrate 12. The metal layer is etched to form metal leads 16, exposing portions of the substrate 12. A disposable liquid 18 is deposited on the metal leads 16 and the exposed portions of substrate 12, and a top portion of the disposable liquid 18 is removed to lower the disposable liquid 18 to at least the tops of the leads 16. A porous silica precursor film 20 is deposited on the disposable liquid 18 and over the tops of the leads 16. The porous silica precursor film 20 is gelled to form a low-porosity silica film 24. The disposable liquid 18 is removed through the low-porosity silica film 24 to form air gaps 22 between metal leads 16 beneath the low-porosity silica film 24. The air gaps 22 have a low dielectric constant and result in reduced capacitance between the metal leads and decreased power consumption.
摘要翻译：一种用于在半导体器件的金属引线16之间形成气隙22的方法。金属层沉积在基底12上。金属层被蚀刻以形成金属引线16，暴露基底12的部分。一次性液体18沉积在金属引线16和基底12的暴露部分上，顶部去除一次性液体18的一部分以将一次性液体18降低到至少引线16的顶部。多孔二氧化硅前体膜20沉积在一次性液体18上并在引线16的顶部上。多孔二氧化硅前体膜20凝胶化以形成低孔隙率二氧化硅膜24.一次性液体18通过低孔隙率二氧化硅膜24去除，以在低孔隙率二氧化硅膜24下面的金属引线16之间形成气隙22。气隙22 具有低介电常数，并且导致金属引线之间的电容降低并降低功耗。

79. 发明授权

US5641711A Low dielectric constant insulation in VLSI applications 失效
标题翻译： VLSI应用中的低介电常数绝缘
公开(公告)号：US5641711A
公开(公告)日：1997-06-24
申请号：US234443
申请日：1994-04-28
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/31 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/46
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76834 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.
摘要翻译：一种用于在连接层上的相邻导体之间减小电容的半导体器件和工艺。这种技术最适用于窄导体间距（小于1微米），其中需要较低介电常数的层间绝缘材料加速。电介质层14相对于半导体衬底10的平面以锐角的方向沉积在狭窄间隔的导体12的顶部之间形成桥，导致形成一个或多个气体介质区域18.该工艺是自对准，使用导体本身的阴影效应来掩蔽电介质材料在它们之间的沉积，以及只有紧密间隔的导体之间的桥接。层间电介质20的随后的沉积完成典型的结构。定向沉积法例如可以是诸如SiO 2，Si 3 N 4，聚酰亚胺或非晶特氟隆的材料的电子束蒸发。

80. 发明授权

US5638599A Method of fabricating hybrid uncooled infrared detectors 失效
标题翻译：混合非制冷红外探测器的制造方法
公开(公告)号：US5638599A
公开(公告)日：1997-06-17
申请号：US412662
申请日：1995-03-29
申请人： Howard R. Beratan , Chih-Chen Cho , Scott R. Summerfelt
发明人： Howard R. Beratan , Chih-Chen Cho , Scott R. Summerfelt
IPC分类号： H01L27/146 , H01L37/02 , H01R9/00
CPC分类号： H01L27/1465 , H01L37/02 , Y10T29/49169
摘要： Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.
摘要翻译：包括多孔材料64的隔热台面36用于将感测集成电路44与未经IR的IR检测器混合系统30的像素34热绝缘。多孔材料64优选为二氧化硅干凝胶。台面36还可以包括保护膜66。

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