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71. 发明授权

US08609505B2 Method of forming MIM capacitor structure in FEOL 有权
标题翻译：在FEOL中形成MIM电容器结构的方法
公开(公告)号：US08609505B2
公开(公告)日：2013-12-17
申请号：US13359032
申请日：2012-01-26
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L27/06 , H01L27/07 , H01L21/20
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译：电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器由第二电容器板，电容器电介质层和半导体衬底形成。

72. 发明授权

US08528397B2 Hermeticity sensor and related method 有权
标题翻译：密封传感器及相关方法
公开(公告)号：US08528397B2
公开(公告)日：2013-09-10
申请号：US12858961
申请日：2010-08-18
申请人： Anthony K. Stamper
发明人： Anthony K. Stamper
IPC分类号： G01L5/00
CPC分类号： G01M3/045 , G01M3/047 , G01M3/186
摘要： A hermeticity sensor for a device includes a beam positioned within a substantially hermetically sealed cavity. The beam includes a stress that changes in response to being exposed to ambient from outside the cavity. A related method is also provided.
摘要翻译：用于装置的气密传感器包括位于基本上密封的空腔内的梁。梁包括响应于从外部暴露于环境的应力。还提供了相关的方法。

73. 发明申请

US20130200521A1 INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL 有权
标题翻译：电感和接线结构与有限的材料制成
公开(公告)号：US20130200521A1
公开(公告)日：2013-08-08
申请号：US13367895
申请日：2012-02-07
申请人： Hanyi Ding , Jeffrey P. Gambino , Zhong-Xiang He , Alvin J. Joseph , Anthony K. Stamper , Timothy D. Sullivan
发明人： Hanyi Ding , Jeffrey P. Gambino , Zhong-Xiang He , Alvin J. Joseph , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L23/5227 , H01L23/5283 , H01L23/53223 , H01L23/645 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.
摘要翻译：后端（BEOL）布线结构和电感器，BEOL布线结构和电感器的制造方法以及BEOL布线结构或电感器的设计结构。形成可以是沟槽或导线的特征，其包括与电介质层的顶表面相交的侧壁。表面层形成在特征的侧壁上。表面层由导体构成，其厚度被选择为提供用于传导高频信号的低电阻路径。

74. 发明授权

US08487401B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08487401B2
公开(公告)日：2013-07-16
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L23/522
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

75. 发明申请

US20120208332A1 SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE 有权
公开(公告)号：US20120208332A1
公开(公告)日：2012-08-16
申请号：US13454709
申请日：2012-04-24
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

76. 发明授权

US08236663B2 Dual-damascene process to fabricate thick wire structure 有权
标题翻译：双镶嵌工艺制造粗线结构
公开(公告)号：US08236663B2
公开(公告)日：2012-08-07
申请号：US12564482
申请日：2009-09-22
申请人： Douglas D. Coolbaugh , Keith E. Downes , Peter J Lindgren , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Keith E. Downes , Peter J Lindgren , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76813 , H01L21/76832 , H01L23/5223 , H01L28/60 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
摘要翻译：一种方法和半导体器件。在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

77. 发明申请

US20120174046A1 METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT 失效
标题翻译：用于补偿集成电路结构变化的方法
公开(公告)号：US20120174046A1
公开(公告)日：2012-07-05
申请号：US13412725
申请日：2012-03-06
申请人： Santo Credendino , Michael D. Hulvey , Jothimalar Kuppusamy , Robert Kenneth Leidy , Paul William Pastel , Bruce Walter Porth , Anthony K. Stamper
发明人： Santo Credendino , Michael D. Hulvey , Jothimalar Kuppusamy , Robert Kenneth Leidy , Paul William Pastel , Bruce Walter Porth , Anthony K. Stamper
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/144 , G03F1/36
摘要： A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying a rules-based optical proximity correction to the selected region of the mask design shape.
摘要翻译：一种补偿集成电路结构变化的方法。该方法包括（a）选择掩模设计形状并选择掩模设计形状的区域; （b）对所有掩模设计形状应用基于模型的光学邻近校正; 以及（b）之后，（c）对掩模设计形状的选定区域应用基于规则的光学邻近校正。

78. 发明授权

US08207568B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08207568B2
公开(公告)日：2012-06-26
申请号：US11162661
申请日：2005-09-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/92
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：制造MIM电容器和MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

79. 发明申请

US20120153434A1 METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY 有权
标题翻译：具有高电容密度的金属绝缘体 - 金属电容器
公开(公告)号：US20120153434A1
公开(公告)日：2012-06-21
申请号：US12969004
申请日：2010-12-15
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Anthony K. Stamper
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/82 , H01L23/5223 , H01L27/0207 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.
摘要翻译：金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

80. 发明申请

US20120137515A1 THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
标题翻译：通过具有循环校正方法的WAVER VIAS
公开(公告)号：US20120137515A1
公开(公告)日：2012-06-07
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

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