会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 71. 发明授权
    • Low offset automatic frequency tuning circuits for continuous-time filter
    • 低偏移自动频率调谐电路,用于连续时间滤波
    • US06400932B1
    • 2002-06-04
    • US09454389
    • 1999-12-03
    • Chang Jun OhJong Kee KwonJong Ryul LeeWon Chul SongHee Bum JungKyung Soo KimHan Jin ChoOok Kim
    • Chang Jun OhJong Kee KwonJong Ryul LeeWon Chul SongHee Bum JungKyung Soo KimHan Jin ChoOok Kim
    • H04B118
    • H03H11/0422H03L7/06
    • The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.
    • 调谐电路技术领域本发明涉及一种调谐电路,更具体地说涉及一种用于连续时间滤波器的调谐电路,其能够精确地确定Gm值,以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化, 时间过滤器。 根据本发明,提供了一种频率调谐电路,其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置,用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样,并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置,用于通过将从外部输入的时钟分频,将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号, 从积分装置获取值,并比较这些信号的实际交点和目标交点; 以及控制装置,用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差,产生控制信号以调节积分装置和偏移采样装置的Gm值。
    • 73. 发明授权
    • Hadamard code generation circuit
    • 哈达玛码生成电路
    • US6069574A
    • 2000-05-30
    • US138545
    • 1998-08-24
    • Ik Soo EoKwang Il YeonKyung Soo Kim
    • Ik Soo EoKwang Il YeonKyung Soo Kim
    • H03K3/84H04J11/00H04J13/00H04J13/12H04L23/00H03M7/00G06K9/36G06F15/332
    • H04J13/0048H04J13/10H04B1/707
    • A hadamard code generation circuit is disclosed. The circuit includes a start reset signal generator for generating a start reset signal START.sub.-- RESET when a 6-bit output signal REF.sub.-- C from the 6-bit reference counter, a higher 4-bit index output signal H(5:2) of the 6-bit register and a 2-bit value from a ground circuit are identical; a "0" value force allocation unit for outputting a FORCE.sub.-- 0.sub.-- DEL signal for forcibly allocating all values of the 0th column to "0" when a 4-bit output signal REF.sub.-- C (5:2) from the 6-bit reference counter and a 4-bit value from the ground circuit are identical; a 2-bit counter for receiving the start reset signal and an external clock signal, outputting lowest bit signals C1 and C0 and outputting a carry-out signal; a 4-bit counter operated in accordance with a result that an inverted FORCE.sub.-- 0 signal and a carry-out signal are ANDed and outputting higher bit signals C4, C3 and C2; a 4th hadamard code generator for logically processing a lower 2-bit output signal from the 2-bit counter and a lower 2-bit index value from the 6-bit register and generating a 4-th hadamard code; a 12th paley code generator for generating a 12th paley code using an output signal from the counter and the FORCE.sub.-- 0.sub.-- DEL signal and the ALL.sub.-- ZERO signal; and a 48th hadamard code generator for logically processing a 4th hadamard code and a 12th paley code and generating a 48th hadamard code.
    • 公开了一种hasamard代码生成电路。 该电路包括一个启动复位信号发生器,当来自6位参考计数器的6位输出信号REF-C,较高的4位索引输出信号H(5:2)为 6位寄存器和来自接地电路的2位值相同; 一个“0”值分配单元,用于当来自6位的4位输出信号REF-C(5:2)时输出用于强制分配第0列的所有值的FORCE-0-DEL信号为“0” 参考计数器和来自接地电路的4位值相同; 用于接收起始复位信号的2位计数器和外部时钟信号,输出最低位信号C1和C0并输出进位信号; 根据反相FORCE-0信号和进位信号进行AND运算并输出较高位信号C4,C3和C2的4位计数器; 用于逻辑处理来自2位计数器的较低2位输出信号和来自6位寄存器的较低2位索引值的第4个哈达马斯代码发生器,并生成第4个哈达玛码; 用于使用来自计数器的输出信号和FORCE-0-DEL信号和ALL-ZERO信号来产生第12个Paley码的第12个Paley码发生器; 以及第48个hasamard代码生成器,用于逻辑处理第4个hadamard代码和第12个paley代码,并生成第48个hasamard代码。
    • 74. 发明授权
    • Apparatus for performing modular multiplication
    • 用于执行模数乘法的装置
    • US5954788A
    • 1999-09-21
    • US984505
    • 1997-12-03
    • Chung Wook SuhSeok Won JungKyung Soo Kim
    • Chung Wook SuhSeok Won JungKyung Soo Kim
    • G06F7/72
    • G06F7/722
    • An apparatus for performing a modular multiplication, including a multiplicand register storing a multiplicand; a multiplier register storing a multiplier; a multiplier word counter counting the number of words of the multiplier register; a partial product calculator calculating a partial product for each word of an output of the multiplicand register and an output of the multiplier register; a first adder adding an output of the partial product calculator to an output of a left word shifter; a quotient estimation calculator estimating a quotient from an output of the first adder and an output of an N modular register; a multiplier multiplying an output of the 2N modular register from an output of the quotient estimation calculator; a multiplexer selecting one of an output of the multiplier and the output of the N modular register from an output of the multiplier word counter; a subtracter subtracting an output of the multiplexer from the output of the first adder; the left word shifter shifting an output of the subtracter to left by one word; and a result register storing the output of the subtracter.
    • 一种用于执行模乘的装置,包括存储被乘数的被乘数寄存器; 存储乘法器的乘法器寄存器; 乘数字计数器,用于计数乘数寄存器的字数; 计算乘法器寄存器的输出的每个字的部分积和乘法器寄存器的输出的部分积计算器; 第一加法器,将所述部分积计算器的输出与左字移位器的输出相加; 商估计计算器从第一加法器的输出和N模寄存器的输出估计商; 乘法器将2N模块寄存器的输出与商估计计算器的输出相乘; 多路复用器从乘法器字计数器的输出中选择乘法器的输出和N模寄存器的输出之一; 减法器,从所述第一加法器的输出减去所述多路复用器的输出; 左字移位器将减法器的输出向左移动一个字; 以及存储减法器的输出的结果寄存器。
    • 76. 发明授权
    • Method for PDU reordering in wireless communication system
    • 无线通信系统中PDU重排序方法
    • US08611374B2
    • 2013-12-17
    • US13120277
    • 2009-03-20
    • Nak Woon SungKyung Soo Kim
    • Nak Woon SungKyung Soo Kim
    • H04J3/24
    • H04L47/32H04L1/1841H04L47/29H04L49/90H04L49/9094
    • The present invention relates to a protocol data unit (PDU) reordering method in a wireless communication system. The terminal maintains the number of bytes of PDUs stored in the buffer for reordering PDUs received in a sequence that is changed due to HARQ error correction to thereby prevent overflow of the reordering buffer. When the HARQ function unit transmits a PDU received at the radio access control RAS (S101), the PDU reordering unit of the access terminal sets a current frame number as an arrival frame number of the received PDU (S102). When a current frame number is stored as an arrival frame number of a received frame, the PDU reordering unit compares a sequence number (SN) of a received PDU with a sequence number of a PDU that is about to be reordered (S 103). If the PDU has already been reordered, the received PDU is discarded (S 104). Else, the PDU reordering unit calculates an average size of a buffer that is required for storing the received PDU by using a moving average calculation equation (S 105).
    • 本发明涉及无线通信系统中的协议数据单元(PDU)重排序方法。 终端维护存储在缓冲器中的PDU的字节数,用于重新排序由于HARQ纠错而改变的序列中接收的PDU,从而防止重新排序缓冲器的溢出。 当HARQ功能单元发送在无线接入控制RAS中接收到的PDU(S101)时,接入终端的PDU重新排序单元设定当前帧号作为接收到的PDU的到达帧号(S102)。 当存储当前帧号作为接收帧的到达帧号时,PDU重新排序单元将接收的PDU的序列号(SN)与要重新排序的PDU的序列号进行比较(S103)。 如果PDU已被重新排序,则接收到的PDU被丢弃(S104)。 否则,PDU重新排序单元通过使用移动平均计算方程来计算存储接收的PDU所需的缓冲器的平均大小(S105)。
    • 80. 发明申请
    • INK JET PRINTER MODULE AND PRINTER USING THE SAME
    • 喷墨打印机模块和打印机使用相同
    • US20110193919A1
    • 2011-08-11
    • US13123674
    • 2009-10-12
    • Kwang Choon ChungHae-Sung JungKi Yong KimKyung Soo KimSung Chul JeonChung II Kim
    • Kwang Choon ChungHae-Sung JungKi Yong KimKyung Soo KimSung Chul JeonChung II Kim
    • B41J2/175
    • B41J2/175B41J2/16552B41J2/1707B41J2/17596
    • An ink jet printer module is disclosed, which comprises a module body which forms an outer structure of the module; an ink inlet port, a washing liquid inlet port and a pneumatic inlet port which are provided at the module body and are connected with the main ink tank, the washing liquid tank and the pneumatic pump, respectively; an ink flow path, a washing liquid flow path, and a pneumatic flow path which are provided in the interior of the module body and communicate with the ink inlet port, the washing liquid inlet port and the pneumatic inlet port, respectively; a common flow path which is provided in the interior of the module body and selectively communicates with either the washing liquid flow path or the washing liquid flow path, so that the pneumatic and washing liquid can be selectively inputted; an ink opening and closing valve which is provided at the module body for controlling the opening and closing of the ink flow path; a pneumatic and washing liquid selection valve which is provided in the module body and controls either the pneumatic or the washing liquid to be selectively inputted into the common low path; an ink discharge port which is provided in the module body and discharges the ink of the ink flow path to the outside of the module body in accordance with a control of the ink opening and closing valve; and a common discharge port which is provided in the module body and discharges either the pneumatic or the washing liquid of the common flow path to the outside of the module body in accordance with a control of the pneumatic and washing liquid selection valve.
    • 公开了一种喷墨打印机模块,其包括形成模块的外部结构的模块体; 分别设置在模块体上的墨水入口,洗涤液入口和气动入口,并分别与主墨罐,洗涤液罐和气动泵连接; 墨水流路,洗涤液流路和气流路径,分别设置在模块主体的内部,并与墨水入口,洗涤液入口和气动进气口连通; 设置在模块主体的内部并选择性地与洗涤液流路或洗涤液流路连通的公共流路,能够选择性地输入气动洗涤液; 油墨打开和关闭阀,设置在模块主体处,用于控制油墨流动通道的打开和关闭; 气动和洗涤液选择阀,其设置在模块主体中并且控制要选择性地输入到公共低通路中的气动或洗涤液体; 油墨排出口,其设置在所述模块主体中,并根据所述油墨开闭阀的控制将所述油墨流路的油墨排出到所述模块体的外部; 以及公共排出口,其设置在模块主体中,并根据气动和洗涤液体选择阀的控制将共用流路的气动或洗涤液体排出到模块体的外部。