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71. 发明授权

US07159205B1 Use of non-lithographic shrink techniques for fabrication/making of imprints masks 失效
标题翻译：使用非光刻收缩技术制造/制作印记掩模
公开(公告)号：US07159205B1
公开(公告)日：2007-01-02
申请号：US10838830
申请日：2004-05-04
申请人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
发明人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
IPC分类号： G06F17/50
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , G03F7/40
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.
摘要翻译：本发明一般涉及光刻系统和方法，更具体地涉及在压印掩模中在图案线形成期间促进改进的临界尺寸（CD）控制和减少线边缘粗糙度（LER）的系统和方法。本发明的一个方面提供了形成具有大于掩模抗蚀剂中最终期望的CD的特征。在施加非光刻收缩技术时，LER被减轻并且CD被减小到期望的目标公差内。

72. 发明授权

US07148142B1 System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权
标题翻译：用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化
公开(公告)号：US07148142B1
公开(公告)日：2006-12-12
申请号：US10874500
申请日：2004-06-23
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A. Phan
IPC分类号： H01L21/44
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76817 , H01L2221/1021
摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.
摘要翻译：提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。电介质蚀刻将图案从转印层转移到电介质层中。然后，金属填充过程用金属填充介电层的双镶嵌开口。

73. 发明授权

US06171737B2 Low cost application of oxide test wafer for defect monitor in photolithography process 失效
标题翻译：用于光刻工艺中缺陷监测器的氧化物测试晶片的低成本应用
公开(公告)号：US06171737B2
公开(公告)日：2001-01-09
申请号：US09017695
申请日：1998-02-03
申请人： Khoi A. Phan , Shobhana R. Punjabi , Robert J. Chiu , Bhanwar Singh
发明人： Khoi A. Phan , Shobhana R. Punjabi , Robert J. Chiu , Bhanwar Singh
IPC分类号： G03F900
CPC分类号： G03F7/7065 , H01L22/20 , H01L22/34
摘要： A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel. An optical review station and scanning electron microscope system are used to review defect and classify defect types. The test wafer can then be reused by cleaning the photolithographic pattern by removing the photoresist, and then removing polymer particles adhering to the oxide layer following removal of the photoresist.
摘要翻译：在亚微米集成电路制造环境中用于检测光刻工艺中的缺陷的低成本技术将使用可重复使用的测试晶片与在线处理相结合，以使用模式比较器系统来监测缺陷。使用规定的光刻制造工艺对具有覆盖在硅衬底上并具有与用于光刻的曝光波长的最小反射率相对应的厚度的可重复使用的测试晶片图案化以根据规定的设计产品规则形成重复图案。使用具有与通过光刻工艺开发的产品相似的设计规则的具有重复图案阵列的掩模版形成图案。然后使用基于图像的检查技术来检查图案化的测试晶片，其中图像具有每像素优选0.25微米的高分辨率像素。光学检查站和扫描电子显微镜系统用于检查缺陷并分类缺陷类型。然后可以通过除去光致抗蚀剂来清洁光刻图案，然后在去除光致抗蚀剂之后去除粘附到氧化物层上的聚合物颗粒，来重新使用测试晶片。

74. 发明授权

US06222936B1 Apparatus and method for reducing defects in a semiconductor lithographic process 有权
标题翻译：用于减少半导体光刻工艺中的缺陷的装置和方法
公开(公告)号：US06222936B1
公开(公告)日：2001-04-24
申请号：US09394871
申请日：1999-09-13
申请人： Khoi A. Phan , Gurjeet S. Bains , David A. Steele , Jonathan A. Orth , Ramkumar Subramanian
发明人： Khoi A. Phan , Gurjeet S. Bains , David A. Steele , Jonathan A. Orth , Ramkumar Subramanian
IPC分类号： G06K900
CPC分类号： G03F7/70616 , G03F7/7065
摘要： An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
摘要翻译：用于优化光刻工艺的布置使用光集电池系统在硅晶片上形成图案，以模拟半导体产品的实际处理条件。然后使用晶片检查系统检查抗蚀剂图案。在线低电压扫描电子显微镜（SEM）系统评估和分类缺陷类型，实现替代处理规范的生成。然后可以通过在不同晶片上形成图案来测试替代处理规范，然后进行分裂式测试以分析不同晶片上的图案，以与现有的光刻工艺和生产资格进行比较。

75. 发明授权

US5985497A Method for reducing defects in a semiconductor lithographic process 失效
标题翻译：用于减少半导体光刻工艺中的缺陷的方法
公开(公告)号：US5985497A
公开(公告)日：1999-11-16
申请号：US17678
申请日：1998-02-03
申请人： Khoi A. Phan , Gurjeet S. Bains , David A. Steele , Jonathan A. Orth , Ramkumar Subramanian
发明人： Khoi A. Phan , Gurjeet S. Bains , David A. Steele , Jonathan A. Orth , Ramkumar Subramanian
IPC分类号： G03F7/20 , G03F9/00
CPC分类号： G03F7/70616 , G03F7/7065
摘要： An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
摘要翻译：用于优化光刻工艺的布置使用光集电池系统在硅晶片上形成图案，以模拟半导体产品的实际处理条件。然后使用晶片检查系统检查抗蚀剂图案。在线低电压扫描电子显微镜（SEM）系统评估和分类缺陷类型，实现替代处理规范的生成。然后可以通过在不同晶片上形成图案来测试替代处理规范，然后进行分裂式测试以分析不同晶片上的图案，以与现有的光刻工艺和生产资格进行比较。

76. 发明授权

US06665065B1 Defect detection in pellicized reticles via exposure at short wavelengths 有权
标题翻译：通过在短波长下的曝光在斑点状掩模版中的缺陷检测
公开(公告)号：US06665065B1
公开(公告)日：2003-12-16
申请号：US09829195
申请日：2001-04-09
申请人： Khoi A. Phan , Bhanwar Singh , Wolfram Porsche
发明人： Khoi A. Phan , Bhanwar Singh , Wolfram Porsche
IPC分类号： G01N2100
CPC分类号： G01N21/95692
摘要： A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.
摘要翻译：提供了用于检测掩模或掩模版中的潜在缺陷的系统和方法，该缺陷可以随曝光波长的辐射而变化。作为示例，检查掩模或掩模版，暴露于指定波长的辐射，然后再检查。暴露前后的检查结果之间的相关性提供暴露相关缺陷的指示，其可以包括由暴露引起的缺陷生长和/或形成缺陷。为了进一步说明，掩模或掩模版的检查和曝光的组合可以相对于薄膜掩模或掩模版实现，以便检测与使用掩模或掩模版的防护薄膜相关的附加缺陷。

77. 发明授权

US06972576B1 Electrical critical dimension measurement and defect detection for reticle fabrication 失效
标题翻译：电子临界尺寸测量和掩模版制作的缺陷检测
公开(公告)号：US06972576B1
公开(公告)日：2005-12-06
申请号：US10160334
申请日：2002-05-31
申请人： Christopher F. Lyons , Khoi A. Phan , Cyrus E. Tabery , Bhanwar Singh
发明人： Christopher F. Lyons , Khoi A. Phan , Cyrus E. Tabery , Bhanwar Singh
IPC分类号： G01R27/08 , G03F1/00 , G03F1/14 , H01L23/544
CPC分类号： H01L22/34 , G03F1/44 , G03F1/84
摘要： A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The system includes a reticle test system that is capable of applying a voltage to the probe points, measuring the resulting current, calculating the corresponding resistance of the test features, and determining the critical dimensions of the test features. The system is also capable of determining defects based on the resistance measurements. The critical dimension information and defect information can then be used to refine the processes used in the fabrication of subsequent reticles.
摘要翻译：提供了一种用于半导体晶片制造中使用的掩模版的测试系统。该系统包括在半透明基底上具有不透明金属层的掩模版。掩模版包括一个或多个测试特征，其中包含可操作用于电接触的探针点。该系统包括能够对探针点施加电压，测量所得电流，计算相应的测试特征的电阻以及确定测试特征的临界尺寸的光罩测试系统。该系统还能够基于电阻测量来确定缺陷。关键尺寸信息和缺陷信息随后可被用于改进在随后的掩模版的制造中使用的工艺。

78. 发明授权

US06563578B2 In-situ thickness measurement for use in semiconductor processing 有权
公开(公告)号：US06563578B2
公开(公告)日：2003-05-13
申请号：US09824112
申请日：2001-04-02
申请人： Arvind Halliyal , Khoi A. Phan , Bhanwar Singh
发明人： Arvind Halliyal , Khoi A. Phan , Bhanwar Singh
IPC分类号： G02N2100
CPC分类号： H01L21/67253 , C23C14/547 , C23C16/52 , G01B11/0683 , H01L22/26
摘要： A system and method are disclosed for providing in-situ monitoring of thin film thickness, such as by employing a non-destructive optical measurement technique. The monitored film thickness may be employed to help achieve a desired feature film thickness and uniformity across a surface of a substrate. By monitoring film thickness during semiconductor processing, for example, one or more process control parameters may be adjusted to help achieve a desired film thickness and/or uniformity thereof.

79. 发明授权

US07056646B1 Use of base developers as immersion lithography fluid 有权
标题翻译：使用基底显影剂作为浸没光刻液
公开(公告)号：US07056646B1
公开(公告)日：2006-06-06
申请号：US10676749
申请日：2003-10-01
申请人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
发明人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03F7/20
CPC分类号： G03F7/2041 , G03F7/322 , G03F7/70341
摘要： Disclosed are immersion lithography methods involving using a base developer as an immersion lithography fluid. Consequently, it is unnecessary to contact a developer with an irradiated resist after the immersion lithography fluid is removed.
摘要翻译：公开了涉及使用基底显影剂作为浸没光刻流体的浸没式光刻方法。因此，在浸没光刻液被去除之后，不需要将曝光的抗蚀剂接触显影剂。

80. 发明授权

US06753261B1 In-situ chemical composition monitor on wafer during plasma etching for defect control 失效
标题翻译：用于缺陷控制的等离子体蚀刻期间晶片上的原位化学成分监测
公开(公告)号：US06753261B1
公开(公告)日：2004-06-22
申请号：US10052173
申请日：2002-01-17
申请人： Khoi A. Phan , Arvind Halliyal , Bhanwar Singh
发明人： Khoi A. Phan , Arvind Halliyal , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01J37/32935 , H01L21/31116 , H01L21/32136
摘要： One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.
摘要翻译：本发明的一个方面涉及用于在等离子体蚀刻期间在晶片表面处或附近原位监测化学成分以检测缺陷的系统和方法。该方法包括提供半导体衬底的步骤，该半导体衬底包括至少一个顶层，其中所述半导体衬底包括至少一种含化学物质的污染物; 对半导体衬底进行等离子体蚀刻工艺，从而去除顶层的至少一部分; 在等离子体蚀刻工艺期间，使用俄歇电子能谱系统或能量分散X射线分析系统之一检测含化学物质的污染物的存在; 并且如果存在，确定含化学物质的污染物的存在是否超过阈值限度。

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