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71. 发明申请

US20050282325A1 Structure and method to improve channel mobility by gate electrode stress modification 审中-公开
公开(公告)号：US20050282325A1
公开(公告)日：2005-12-22
申请号：US11201163
申请日：2005-08-11
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

72. 发明申请

US20050264320A1 LOGIC CIRCUITS HAVING LINEAR AND CELLULAR GATE TRANSISTORS 失效
标题翻译：具有线性和细胞栅极晶体管的逻辑电路
公开(公告)号：US20050264320A1
公开(公告)日：2005-12-01
申请号：US10709784
申请日：2004-05-27
申请人： Victor Chan , Hsing-Jen Wann , Shih-Fen Huang , Oleg Gluschenkov
发明人： Victor Chan , Hsing-Jen Wann , Shih-Fen Huang , Oleg Gluschenkov
IPC分类号： H01L27/02 , H03K17/16 , H03K19/017 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/0948 , H01L27/0203 , H03K19/01707
摘要： A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.
摘要翻译：逻辑电路设置有具有驱动第一电容性负载的多个线性栅极晶体管的第一反相器和驱动第二电容负载的多个蜂窝状栅极晶体管的第二反相器。第一个逆变器串联连接到第二个逆变器。第二容性负载大于第一容性负载。

73. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

74. 发明申请

US20050189589A1 HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 有权
标题翻译：混合SOI / BULK半导体晶体管
公开(公告)号：US20050189589A1
公开(公告)日：2005-09-01
申请号：US10708378
申请日：2004-02-27
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L27/01 , H01L29/06 , H01L29/10 , H01L29/786
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

75. 发明申请

US20050148146A1 High performance strained CMOS devices 失效
标题翻译：高性能应变CMOS器件
公开(公告)号：US20050148146A1
公开(公告)日：2005-07-07
申请号：US11060784
申请日：2005-02-18
申请人： Bruce Doris , Oleg Gluschenkov
发明人： Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L20060101 , H01L21/336 , H01L21/76 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/78 , H01L29/7846
摘要： A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.
摘要翻译：一种半导体器件和制造方法提供一种具有浅沟槽隔离的n沟道场效应晶体管（nFET），其具有在与电流流动方向平行的方向上突出Si-SiO 2界面; 在横向于电流的方向上。器件和方法还提供具有浅沟槽隔离的p沟道场效应晶体管（pFET），其具有在横向于电流的方向上突出Si-SiO 2界面的突出端。然而，pFET的浅沟槽隔离在平行于电流方向的方向上没有突出端。

76. 发明申请

US20050106799A1 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 失效
标题翻译：具有颗粒半导体材料的应力半导体器件结构
公开(公告)号：US20050106799A1
公开(公告)日：2005-05-19
申请号：US10707018
申请日：2003-11-14
申请人： Bruce Doris , Michael Belyansky , Diane Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce Doris , Michael Belyansky , Diane Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

77. 发明申请

US20050104131A1 Silicon device on Si:C-OI and SGOI and method of manufacture 有权
标题翻译： Si：C-OI和SGOI上的硅器件及其制造方法
公开(公告)号：US20050104131A1
公开(公告)日：2005-05-19
申请号：US10715400
申请日：2003-11-19
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/24 , H01L29/808 , H01L29/10 , H01L27/01 , H01L29/00 , H01L31/036
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

78. 发明申请

US20050093081A1 OXIDATION METHOD FOR ALTERING A FILM STRUCTURE AND CMOS TRANSISTOR STRUCTURE FORMED THEREWITH 失效
标题翻译：用于改造薄膜结构的氧化方法和形成的CMOS晶体管结构
公开(公告)号：US20050093081A1
公开(公告)日：2005-05-05
申请号：US10605889
申请日：2003-11-04
申请人： Michael Belyansky , Diane Boyd , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Diane Boyd , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

79. 发明授权

US06720630B2 Structure and method for MOSFET with metallic gate electrode 有权
标题翻译：具有金属栅电极的MOSFET的结构和方法
公开(公告)号：US06720630B2
公开(公告)日：2004-04-13
申请号：US09867874
申请日：2001-05-30
申请人： Jack A. Mandelman , Oleg Gluschenkov , Carl J. Radens
发明人： Jack A. Mandelman , Oleg Gluschenkov , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L21/28247 , H01L29/4933 , H01L29/6653 , H01L29/66545 , H01L29/6659 , Y10S257/90
摘要： A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.
摘要翻译：提供一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法，该金属氧化物半导体场效应晶体管（MOSFET）具有金属栅电极，其在随后的栅极氧化处理期间被悬挂的侧壁间隔物保护。还提供了通过本发明方法形成的半导体结构。具体地，本发明的半导体结构包括半导体衬底，其包括形成在图案化栅极电介质上的图案化栅极区域，所述图案化栅极区域至少包括形成在多晶硅栅电极顶部的金属栅电极; 形成在包括金属栅极的图案化栅极区域的上部上的悬挂侧壁间隔物; 以及形成在图案化栅极区域的下部上的热氧化物层，其包括多晶硅栅电极的一部分而不是金属栅电极。

80. 发明授权

US06709926B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06709926B2
公开(公告)日：2004-03-23
申请号：US10160540
申请日：2002-05-31
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有以最小光刻特征尺寸分隔的阵列晶体管的存储单元，以及由扩散阻挡层封装的非硅化金属位线，而高性能逻辑晶体管可以形成在同一芯片上，而不会损害性能，包括有效沟道硅化触点低源极/漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅极电介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过易平坦化的材料实现，并且使用平坦化为不同材料的结构的高度的类似掩模来去耦合逻辑晶体管中的衬底和栅极注入。

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