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71. 发明申请

US20090278185A1 DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY 失效
标题翻译：非易失性随机访问存储器的存储单元的设备结构和非易失性随机存取存储器的设计结构
公开(公告)号：US20090278185A1
公开(公告)日：2009-11-12
申请号：US12118241
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L29/00 , G06F9/455
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.
摘要翻译：非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。半导体本体包括源极，漏极以及源极和漏极之间的沟道。浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。第一电介质层设置在半导体本体的沟道和浮栅之间。第二介电层设置在控制栅电极和浮栅电极之间。

72. 发明授权

US07615828B2 CMOS devices adapted to prevent latchup and methods of manufacturing the same 失效
标题翻译：适于防止闭锁的CMOS器件及其制造方法
公开(公告)号：US07615828B2
公开(公告)日：2009-11-10
申请号：US11456357
申请日：2006-07-10
申请人： Jack A. Mandelman , William R. Tonti
发明人： Jack A. Mandelman , William R. Tonti
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7833 , H01L21/743 , H01L21/823814 , H01L21/823878 , H01L27/0921 , H01L29/665 , H01L2027/1189
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是衬底上的半导体器件，其包括：（1）第一金属氧化物半导体场效应晶体管（MOSFET）; （2）耦合到所述第一MOSFET的第二MOSFET，其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管（BJT）; 和（3）将第一或第二MOSFET的源极扩散区域与源极扩散区域下方的掺杂阱区域电耦合的导电区域。导电区域适于防止在环路中形成感应电流。提供了许多其他方面。

73. 发明申请

US20090269903A1 METHODS FOR FABRICATING ACTIVE DEVICES ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE UTILIZING MULTIPLE DEPTH SHALLOW TRENCH ISOLATIONS 失效
标题翻译：在使用多个深度深层分离分离的半导体绝缘体基板上制作活性器件的方法
公开(公告)号：US20090269903A1
公开(公告)日：2009-10-29
申请号：US12108851
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L21/7624
摘要： Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.
摘要翻译：在绝缘体上半导体衬底中制造器件结构的方法。该方法包括在衬底器件层中形成第一隔离区，该第一隔离区从器件层的顶表面延伸到第一深度，并且在半导体层中形成第二隔离区，该半导体层从半导体层的顶表面延伸到第二隔离区深度大于第一深度。该方法还包括在垂直位于第一隔离区域和绝缘层之间的半导体层中形成器件结构的掺杂区域。

74. 发明申请

US20090206447A1 ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
标题翻译：抗保护器件结构和电镀电路结构与方法
公开(公告)号：US20090206447A1
公开(公告)日：2009-08-20
申请号：US12031761
申请日：2008-02-15
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

75. 发明申请

US20090134463A1 SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
标题翻译：用于制造集成电路芯片的半导体结构和系统
公开(公告)号：US20090134463A1
公开(公告)日：2009-05-28
申请号：US12348344
申请日：2009-01-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
摘要翻译：一种半导体结构和用于制造集成电路芯片的系统。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

76. 发明授权

US07381610B2 Semiconductor transistors with contact holes close to gates 有权
标题翻译：具有靠近门的接触孔的半导体晶体管
公开(公告)号：US07381610B2
公开(公告)日：2008-06-03
申请号：US11163966
申请日：2005-11-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , William R. Tonti
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114
摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.
摘要翻译：一种结构及其形成方法。该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

77. 发明授权

US07336095B2 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US07336095B2
公开(公告)日：2008-02-26
申请号：US11760575
申请日：2007-06-08
申请人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： H03K19/00
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

78. 发明申请

US20080029844A1 ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE 审中-公开
标题翻译：防腐结构选择性地与保护环结构集成
公开(公告)号：US20080029844A1
公开(公告)日：2008-02-07
申请号：US11462070
申请日：2006-08-03
申请人： James W. Adkisson , Jeffrey P. Gambino , Kirk D. Peterson , William R. Tonti
发明人： James W. Adkisson , Jeffrey P. Gambino , Kirk D. Peterson , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor layer is located within the first aperture and a second conductor layer is located within the second aperture. At least a first anti-fuse material layer contacts the first conductor layer. The first conductor layer and the second conductor layer may comprise doped conductor materials that upon fusing of the anti-fuse structure provide an anti-fuse diode or an anti-fuse resistor.
摘要翻译：用于制造抗熔丝结构的反熔丝结构和相关方法包括半导体衬底内的掺杂阱。暴露掺杂阱的第一孔径和第二孔径位于位于半导体衬底和掺杂阱上方的电介质层内。第一导体层位于第一孔内，第二导体层位于第二孔内。至少第一反熔丝材料层接触第一导体层。第一导体层和第二导体层可以包括掺杂的导体材料，其在抗熔丝结构融合时提供抗熔丝二极管或抗熔丝电阻器。

79. 发明授权

US07227230B2 Low-K gate spacers by fluorine implantation 有权
标题翻译：通过氟注入的低K栅间隔
公开(公告)号：US07227230B2
公开(公告)日：2007-06-05
申请号：US10775440
申请日：2004-02-10
申请人： Jeffrey P. Gambino , Jack Mandelman , William R. Tonti
发明人： Jeffrey P. Gambino , Jack Mandelman , William R. Tonti
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26586 , H01L21/31155 , H01L29/4983 , H01L29/6656 , Y10S257/90
摘要： A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
摘要翻译： MOSFET器件和制造具有通过氟注入产生的低K电介质氧化物栅极侧壁间隔物的MOSFET器件的方法。本发明将氟注入到栅极氧化物侧壁间隔物中，其用于改变高级复合栅极电介质的性质，例如，氮化的氧化物，NO和栅极侧壁电介质，使得氟的低K特性用于开发低寄生电容MOSFET。

80. 发明授权

US07215002B2 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US07215002B2
公开(公告)日：2007-05-08
申请号：US11051703
申请日：2005-02-04
申请人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
发明人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

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