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71. 发明授权

US08440259B2 Vapor based combinatorial processing 有权
公开(公告)号：US08440259B2
公开(公告)日：2013-05-14
申请号：US12013729
申请日：2008-01-14
申请人： Tony P. Chiang , Sunil Shanker , Chi-I Lang
发明人： Tony P. Chiang , Sunil Shanker , Chi-I Lang
IPC分类号： C23C16/00
CPC分类号： C23C16/45574 , C23C16/45544 , C23C16/45548
摘要： A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.

72. 发明授权

US08432177B2 High throughput current-voltage combinatorial characterization tool and method for combinatorial solar test substrates 有权
公开(公告)号：US08432177B2
公开(公告)日：2013-04-30
申请号：US12952983
申请日：2010-11-23
申请人： Yun Wang , Tony P. Chiang , Chi-I Lang
发明人： Yun Wang , Tony P. Chiang , Chi-I Lang
IPC分类号： G01R31/26
CPC分类号： G01R31/26 , G01N21/55 , G01R31/2607 , H02S50/10
摘要： Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

73. 发明授权

US08426970B2 Substrate processing including a masking layer 有权
公开(公告)号：US08426970B2
公开(公告)日：2013-04-23
申请号：US12979627
申请日：2010-12-28
申请人： Zachary Fresco , Chi-I Lang , Sandra G. Malhotra , Tony P. Chiang , Thomas R. Boussie , Nitin Kumar , Jinhong Tong , Anh Duong
发明人： Zachary Fresco , Chi-I Lang , Sandra G. Malhotra , Tony P. Chiang , Thomas R. Boussie , Nitin Kumar , Jinhong Tong , Anh Duong
IPC分类号： H01L23/52 , H01L23/532
CPC分类号： H01L21/288 , B82Y30/00 , H01L21/3105 , H01L21/31058 , H01L21/76834 , H01L21/76849 , H01L21/7685
摘要： Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

74. 发明授权

US08383430B2 Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 失效
标题翻译：用于在半导体衬底上筛选多个样品的组合处理方法
公开(公告)号：US08383430B2
公开(公告)日：2013-02-26
申请号：US13399719
申请日：2012-02-17
申请人： Guarav Verma , Tony P. Chiang , Imran Hashim , Sandra G Malhotra , Prashant B Phatak , Kurt H Weiner
发明人： Guarav Verma , Tony P. Chiang , Imran Hashim , Sandra G Malhotra , Prashant B Phatak , Kurt H Weiner
IPC分类号： H01L21/00
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

75. 发明授权

US08372759B2 Molecular self-assembly in substrate processing 有权
标题翻译：基板加工中的分子自组装
公开(公告)号：US08372759B2
公开(公告)日：2013-02-12
申请号：US13045298
申请日：2011-03-10
申请人： David E. Lazovsky , Tony P. Chiang , Majid Keshavarz
发明人： David E. Lazovsky , Tony P. Chiang , Majid Keshavarz
IPC分类号： H01L21/469
CPC分类号： H01L23/5329 , B82Y30/00 , H01L21/31 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76873 , H01L21/76879 , H01L28/65 , H01L29/06 , H01L2924/0002 , Y10T428/249953 , H01L2924/00
摘要： Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
摘要翻译：提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟代烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

76. 发明申请

US20130026438A1 CURRENT-LIMITING LAYER AND A CURRENT-REDUCING LAYER IN A MEMORY DEVICE 有权
标题翻译：电流限制层和存储器件中的电流减少层
公开(公告)号：US20130026438A1
公开(公告)日：2013-01-31
申请号：US13399530
申请日：2012-02-17
申请人： Yun Wang , Tony P. Chiang , Imran Hashim
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , G11C11/00 , G11C13/00 , G11C13/0007 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1641
摘要： A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.
摘要翻译：电流限制层和电流减少层被并入到电阻式开关存储器件中以形成存储器阵列。结合的限流层在电阻式开关存储器件的编程期间减少了电流尖峰的发生，并且并入的电流降低层使可流过电阻式开关存储器件的总体电流水平最小化。合并在一起的两个层次有助于提高设备性能和使用寿命。

77. 发明申请

US20120136468A1 Apparatus and Method for Testing Electromigration in Semiconductor Devices 有权
标题翻译：用于测试半导体器件中的电迁移的装置和方法
公开(公告)号：US20120136468A1
公开(公告)日：2012-05-31
申请号：US12957346
申请日：2010-11-30
申请人： Yun Wang , Tony P. Chiang , Chi-I Lang
发明人： Yun Wang , Tony P. Chiang , Chi-I Lang
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G01R31/2858
摘要： An apparatus and method for testing electromigration in semiconductor devices includes providing an electromigration test structure, where the electromigration test structure includes a first metal line; a metal bridge operatively coupled to the first metal line; a second metal line operatively coupled to the metal bridge; a barrier layer surrounding the electromigration test structure; current contact pads; and voltage contact pads. The current contact pads are connected to a current source and the voltage contact pads are connected to a voltage source. The barrier layer is exposed to the elevated current density as current travels from the first metal line across the barrier layer through the metal bridge to the second metal line.
摘要翻译：一种用于测试半导体器件中的电迁移的装置和方法，包括提供电迁移测试结构，其中电迁移测试结构包括第一金属线; 操作地连接到第一金属线的金属桥; 可操作地耦合到所述金属桥的第二金属线; 围绕电迁移测试结构的阻挡层; 当前接触垫; 和电压接触垫。当前接触焊盘连接到电流源，并且电压接触焊盘连接到电压源。当电流从第一金属线穿过阻挡层穿过金属桥到第二金属线时，阻挡层暴露于升高的电流密度。

78. 发明授权

US08148273B1 Combinatorial plasma enhanced deposition techniques 有权
公开(公告)号：US08148273B1
公开(公告)日：2012-04-03
申请号：US13337728
申请日：2011-12-27
申请人： Sunil Shanker , Tony P. Chiang
发明人： Sunil Shanker , Tony P. Chiang
IPC分类号： H01L21/31
CPC分类号： C23C16/047 , C23C16/04 , C23C16/45536 , C23C16/45551 , C23C16/45565 , C23C16/45574 , C23C16/45591 , C23C16/4583 , C23C16/46 , C23C16/50 , C23C16/5096 , C23C16/52 , H01J37/32357 , H01J37/32366
摘要： Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

79. 发明申请

US20120074096A1 METHODS FOR DISCRETIZED PROCESSING AND PROCESS SEQUENCE INTEGRATION OF REGIONS OF A SUBSTRATE 有权
公开(公告)号：US20120074096A1
公开(公告)日：2012-03-29
申请号：US13311855
申请日：2011-12-06
申请人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
发明人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
IPC分类号： C23C16/44 , C23F1/02 , C23C16/50
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

80. 发明申请

US20120048829A1 METHODS FOR DISCRETIZED PROCESSING AND PROCESS SEQUENCE INTEGRATION OF REGIONS OF A SUBSTRATE 失效
标题翻译：分离处理方法和基板区域的过程序列整合
公开(公告)号：US20120048829A1
公开(公告)日：2012-03-01
申请号：US13288786
申请日：2011-11-03
申请人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
发明人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
IPC分类号： B05D5/06 , C23C16/44 , C23C16/50 , C23F1/02 , B05D3/10
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

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