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71. 发明授权

US08233341B2 Method and structure for SRAM cell trip voltage measurement 有权
标题翻译： SRAM单元跳闸电压测量的方法和结构
公开(公告)号：US08233341B2
公开(公告)日：2012-07-31
申请号：US12584220
申请日：2009-09-01
申请人： Xiaowei Deng , Wah Kit Loh
发明人： Xiaowei Deng , Wah Kit Loh
IPC分类号： G11C29/50
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5004
摘要： A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor (208) has a current path connected between the complementary terminal and a second access terminal (216) and has a second control terminal connected to the first control terminal. A first pass gate (604) has a current path connected between the first access terminal (214) and a third access terminal (XBLT) and has a third control terminal. A second pass gate (606) has a current path connected between the second access terminal (216) and a fourth access terminal (XBLB) and has a fourth control terminal connected to the third control terminal.
摘要翻译：公开了参数测试电路（图6）。测试电路包括具有真实和互补端子的锁存电路。第一存取晶体管（206）具有连接在真实终端和第一接入终端（214）之间的电流路径，并且具有第一控制终端。第二存取晶体管（208）具有连接在互补端子和第二接入端子（216）之间的电流路径，并且具有连接到第一控制端子的第二控制端子。第一通路门（604）具有连接在第一接入终端（214）和第三接入终端（XBLT）之间的电流路径，并且具有第三控制终端。第二传递门（606）具有连接在第二接入终端（216）和第四接入终端（XBLB）之间的电流路径，并且具有连接到第三控制终端的第四控制终端。

72. 发明申请

US20120106225A1 Array-Based Integrated Circuit with Reduced Proximity Effects 有权
标题翻译：基于阵列的集成电路具有降低接近效应
公开(公告)号：US20120106225A1
公开(公告)日：2012-05-03
申请号：US12913479
申请日：2010-10-27
申请人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Terence G. W. Blake
发明人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Terence G. W. Blake
IPC分类号： G11C5/02 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , G11C5/025 , Y02P90/265
摘要： An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.
摘要翻译：一种用于生成集成电路的布局的集成电路和方法，其中根据类似于单元本身构造的器件在一个或多个结构级别中实现诸如存储器或逻辑单元的重复特征阵列的外围电路。确定在各种水平上引起邻近效应的距离。这些接近效应距离决定了在每个级别的阵列之外和之后重复的那些特征的数量，其中构造外围电路以匹配阵列中的重复特征的构造。

73. 发明申请

US20110273946A1 UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING 有权
标题翻译：通用测试结构基于SRAM片上参数测试模块和操作和测试方法
公开(公告)号：US20110273946A1
公开(公告)日：2011-11-10
申请号：US12774044
申请日：2010-05-05
申请人： Xiaowei Deng , Wah K. Loh
发明人： Xiaowei Deng , Wah K. Loh
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C11/416 , G11C29/12 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C29/54 , G11C2029/5002 , G11C2029/5004 , G11C2029/5006
摘要： An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.
摘要翻译：集成电路片上参数（OCP）测试结构包括具有UTS端口的静态随机存取存储器（SRAM）通用测试结构（UTS），以及被配置为确定SRAM UTS的第一和第二UTS端口以独立连接到第一和第二片上测试焊盘。集成电路OCP测试结构还包括连接到OCP控制器并被配置为将SRAM UTS的第一和第二UTS端口分别连接到第一和第二片上测试焊盘的UTS OCP路由器。还包括操作集成电路OCP测试结构和集成电路的OCP测试的方法。

74. 发明申请

US20110158018A1 Structure and Methods for Measuring Margins in an SRAM Bit 有权
标题翻译： SRAM位测量结构和方法
公开(公告)号：US20110158018A1
公开(公告)日：2011-06-30
申请号：US13043229
申请日：2011-03-08
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C29/12
CPC分类号： G11C8/08 , G11C11/413 , G11C11/419 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.
摘要翻译：使用包括SRAM阵列结构和电路设计效果的操作电路来测量SRAM位的读余量，写余量和稳定裕度的方法。另外，用于测量SRAM的读取余量，写入余量和稳定裕度的方法，排除了SRAM阵列架构和电路设计的影响。

75. 发明申请

US20110013470A1 Structure and Method for Screening SRAMS 有权
标题翻译：筛选SRAMS的结构和方法
公开(公告)号：US20110013470A1
公开(公告)日：2011-01-20
申请号：US12502879
申请日：2009-07-14
申请人： Theodore W. Houston , Xiaowei Deng
发明人： Theodore W. Houston , Xiaowei Deng
IPC分类号： G11C29/00 , G11C8/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12 , G11C2029/1202
摘要： An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.
摘要翻译：包含SRAM的集成电路，其提供开关以在屏蔽期间将SRAM字线电压与SRAM阵列电压分离，并且在SRAM位筛选测试的一部分期间还提供不同的字线和阵列电压。一种用于在SRAM阵列中筛选SRAM位的方法，其中在屏蔽测试的一部分期间字线电压不同于阵列电压。

76. 发明申请

US20100208536A1 Structure and Methods for Measuring Margins in an SRAM bit 有权
标题翻译：用于测量SRAM位中边缘的结构和方法
公开(公告)号：US20100208536A1
公开(公告)日：2010-08-19
申请号：US12388439
申请日：2009-02-18
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C29/00 , G11C7/00 , G11C8/08
CPC分类号： G11C8/08 , G11C11/413 , G11C11/419 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.
摘要翻译：使用包括SRAM阵列结构和电路设计效果的操作电路来测量SRAM位的读余量，写余量和稳定裕度的方法。另外，用于测量SRAM的读取余量，写入余量和稳定裕度的方法，排除了SRAM阵列架构和电路设计的影响。

77. 发明申请

US20090175113A1 CHARACTERIZATION OF BITS IN A FUNCTIONAL MEMORY 有权
标题翻译：功能记忆中位置的表征
公开(公告)号：US20090175113A1
公开(公告)日：2009-07-09
申请号：US12347928
申请日：2008-12-31
申请人： Xiaowei Deng , Wah K. Loh , Theodore W. Houston
发明人： Xiaowei Deng , Wah K. Loh , Theodore W. Houston
IPC分类号： G11C5/14 , G11C8/08 , G11C8/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要： Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port.
摘要翻译：本公开的实施例提供了一种集成电路，其包括功能存储器和表征功能存储器中的存储器单元的组件或缺陷的方法。在一个实施例中，功能存储器包括具有外围源极和吸收电压供给端口的行和列周边单元，以行和列组织的存储器单元的阵列以及由提供对存储器单元的行访问的字线驱动器控制的字线的数组。此外，功能存储器还包括由直接位线访问电路控制的位线，其通过位线模拟访问端口和独立电压供应端口提供对存储器单元的直接位线访问。

78. 发明授权

US07301849B2 System for reducing row periphery power consumption in memory devices 有权
标题翻译：用于减少存储器件中的行周边功耗的系统
公开(公告)号：US07301849B2
公开(公告)日：2007-11-27
申请号：US10618473
申请日：2003-07-11
申请人： Xiaowei Deng , Theodore W. Houston , Bryan D. Sheffield
发明人： Xiaowei Deng , Theodore W. Houston , Bryan D. Sheffield
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/417
摘要： The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.
摘要翻译：本发明提供了一种用于减少半导体存储器件中的行周边功耗的系统，特别是在睡眠模式操作期间。根据本发明的存储器件（100）在存储器单元行之前具有一行（106）存储单元和驱动器电路（102）。本发明提供了一种在靠近该行存储器单元的驱动器电路内实例化的介入电路（114）。在介入电路之前的驱动器电路（108,110）掉电的同时，介入电路被操作以将该行存储器单元保持在期望的状态。

79. 发明授权

US06925025B2 SRAM device and a method of powering-down the same 有权
公开(公告)号：US06925025B2
公开(公告)日：2005-08-02
申请号：US10701669
申请日：2003-11-05
申请人： Xiaowei Deng , Theodore W. Houston
发明人： Xiaowei Deng , Theodore W. Houston
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14
摘要： An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to the SRAM array having voltage domains defined by a boundary and (3) a power-down voltage controller coupled to the SRAM array and the peripheral circuitry that separately regulates voltages of the SRAM array and the peripheral circuitry to reduce leakage current of the SRAM array and the peripheral circuitry at the boundary during a sleep mode.

80. 发明申请

US20050036385A1 System for reducing row periphery power consumption in memory devices 有权
公开(公告)号：US20050036385A1
公开(公告)日：2005-02-17
申请号：US10945725
申请日：2004-09-21
申请人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
发明人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
IPC分类号： G11C8/08 , G11C11/417 , G11C11/34
CPC分类号： G11C8/08 , G11C11/417
摘要： The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

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