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1. 发明授权

US5220534A Substrate bias generator system 失效
标题翻译：基板偏心发电机系统
公开(公告)号：US5220534A
公开(公告)日：1993-06-15
申请号：US560662
申请日：1990-07-31
申请人： Wah K. Loh , Narasimhan Iyengar , Danny R. Cline , Wah K. Loh , Hugh P. McAdams
发明人： Wah K. Loh , Narasimhan Iyengar , Danny R. Cline , Wah K. Loh , Hugh P. McAdams
IPC分类号： G11C11/408 , G05F3/20 , G11C5/14 , H01L21/822 , H01L21/8242 , H01L23/50 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： G11C5/146 , G05F3/205 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L2224/83101 , H01L2924/1305 , H01L2924/181 , H01L2924/3011
摘要： A circuit for providing a bias to the substrate of a dynamic memory device having a memory array and peripheral circuitry formed in a semiconductor substrate is disclosed. The circuit includes a low power pump and oscillator to provide a substrate bias in a memory standby mode. A high power pump and oscillator is included to provide a substrate bias when the memory is active. A booster oscillator and pump to provide a substrate bias when the memory is active and when the substrate voltage level is greater than a preset level is also provided. A method for contolling the voltage level of the substrate upon which a dynamic memory device is formed is also disclosed.

2. 发明授权

US09208899B2 Universal test structures based SRAM on-chip parametric test module and methods of operating and testing 有权
标题翻译：基于通用测试结构的SRAM片上参数测试模块和操作和测试方法
公开(公告)号：US09208899B2
公开(公告)日：2015-12-08
申请号：US12774044
申请日：2010-05-05
申请人： Xiaowei Deng , Wah K. Loh
发明人： Xiaowei Deng , Wah K. Loh
IPC分类号： G11C29/48 , G11C29/54 , G11C29/50 , G11C29/12 , G11C11/416
CPC分类号： G11C29/48 , G11C11/416 , G11C29/12 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C29/54 , G11C2029/5002 , G11C2029/5004 , G11C2029/5006
摘要： An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.
摘要翻译：集成电路片上参数（OCP）测试结构包括具有UTS端口的静态随机存取存储器（SRAM）通用测试结构（UTS），以及被配置为确定SRAM UTS的第一和第二UTS端口以独立连接到第一和第二片上测试焊盘。集成电路OCP测试结构还包括连接到OCP控制器并被配置为将SRAM UTS的第一和第二UTS端口分别连接到第一和第二片上测试焊盘的UTS OCP路由器。还包括操作集成电路OCP测试结构和集成电路的OCP测试的方法。

3. 发明申请

US20110273946A1 UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING 有权
标题翻译：通用测试结构基于SRAM片上参数测试模块和操作和测试方法
公开(公告)号：US20110273946A1
公开(公告)日：2011-11-10
申请号：US12774044
申请日：2010-05-05
申请人： Xiaowei Deng , Wah K. Loh
发明人： Xiaowei Deng , Wah K. Loh
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C11/416 , G11C29/12 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C29/54 , G11C2029/5002 , G11C2029/5004 , G11C2029/5006
摘要： An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.
摘要翻译：集成电路片上参数（OCP）测试结构包括具有UTS端口的静态随机存取存储器（SRAM）通用测试结构（UTS），以及被配置为确定SRAM UTS的第一和第二UTS端口以独立连接到第一和第二片上测试焊盘。集成电路OCP测试结构还包括连接到OCP控制器并被配置为将SRAM UTS的第一和第二UTS端口分别连接到第一和第二片上测试焊盘的UTS OCP路由器。还包括操作集成电路OCP测试结构和集成电路的OCP测试的方法。

4. 发明申请

US20090175113A1 CHARACTERIZATION OF BITS IN A FUNCTIONAL MEMORY 有权
标题翻译：功能记忆中位置的表征
公开(公告)号：US20090175113A1
公开(公告)日：2009-07-09
申请号：US12347928
申请日：2008-12-31
申请人： Xiaowei Deng , Wah K. Loh , Theodore W. Houston
发明人： Xiaowei Deng , Wah K. Loh , Theodore W. Houston
IPC分类号： G11C5/14 , G11C8/08 , G11C8/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要： Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port.
摘要翻译：本公开的实施例提供了一种集成电路，其包括功能存储器和表征功能存储器中的存储器单元的组件或缺陷的方法。在一个实施例中，功能存储器包括具有外围源极和吸收电压供给端口的行和列周边单元，以行和列组织的存储器单元的阵列以及由提供对存储器单元的行访问的字线驱动器控制的字线的数组。此外，功能存储器还包括由直接位线访问电路控制的位线，其通过位线模拟访问端口和独立电压供应端口提供对存储器单元的直接位线访问。

5. 发明授权

US5309446A Test validation method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试验证方法
公开(公告)号：US5309446A
公开(公告)日：1994-05-03
申请号：US927557
申请日：1992-08-06
申请人： Danny R. Cline , Wah K. Loh , Adin E. Hyslop , Hugh P. McAdams , Chok Y. Hung
发明人： Danny R. Cline , Wah K. Loh , Adin E. Hyslop , Hugh P. McAdams , Chok Y. Hung
IPC分类号： G01R31/317 , G06F11/00 , G11C29/00 , G11C29/50 , G01R31/28
CPC分类号： G11C29/781 , G01R31/31701 , G11C29/50 , G06F11/006 , G11C11/401
摘要： A test validation process for a semiconductor device applies signals indicating a test mode to the semiconductor device. The device produces output signals and the output signals are read to determine whether the device is in the indicated test mode. The test mode is conducted by operating the device. The output signals are read upon completion of the test mode to determine if the device is still in the indicated test mode. The test validation method is useful for memory chips and particularly Dynamic Random Access Memory, DRAM, devices that are burn-in stress tested.
摘要翻译：半导体器件的测试验证过程将指示测试模式的信号应用于半导体器件。该器件产生输出信号，读取输出信号以确定器件是否处于指示的测试模式。测试模式通过操作设备进行。在完成测试模式时读取输出信号，以确定设备是否仍处于指示的测试模式。测试验证方法对于内存芯片，特别是动态随机存取存储器，DRAM，被测试的老化压力的器件是有用的。

6. 发明授权

US5923599A Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit 失效
标题翻译：使用内置自检单元在动态随机存取存储器中进行子阵列测试的装置和方法
公开(公告)号：US5923599A
公开(公告)日：1999-07-13
申请号：US840362
申请日：1997-04-29
申请人： Kuong H. Hii , Danny R. Cline , Theo J. Powell , Wah K. Loh
发明人： Kuong H. Hii , Danny R. Cline , Theo J. Powell , Wah K. Loh
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/12 , G11C29/20 , G11C7/00
CPC分类号： G11C29/20
摘要： In a built-in-self-test (BIST) unit or a memory unit, an address limits unit is provided which, prior to initiation of the test procedures, has start and stop addresses stored therein. Upon the initiation of the test procedures by the BIST unit, the start address of the address limits unit is transferred to the address counters units wherein the start address serves as the initial test address. The stop address is transferred to the address counters unit wherein the stop address will be compared with the current address. When the stop address and the current address match, the test procedure being executed by the BIST unit will be terminated. In this manner, any subarray in the memory unit can be selected for test.
摘要翻译：在内置自检（BIST）单元或存储器单元中，提供地址限制单元，其在开始测试程序之前具有存储在其中的起始和停止地址。在由BIST单元开始测试过程时，地址限制单元的起始地址被传送到地址计数器单元，其中起始地址用作初始测试地址。停止地址被传送到地址计数器单元，其中停止地址将与当前地址进行比较。当停止地址和当前地址匹配时，由BIST单元执行的测试程序将被终止。以这种方式，可以选择存储器单元中的任何子阵列进行测试。

7. 发明授权

US5200364A Packaged integrated circuit with encapsulated electronic devices 失效
标题翻译：封装的集成电路与封装的电子设备
公开(公告)号：US5200364A
公开(公告)日：1993-04-06
申请号：US822774
申请日：1992-01-21
申请人： Wah K. Loh
发明人： Wah K. Loh
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49541 , H01L23/49589 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/83101 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , Y10S257/924 , Y10T29/49121
摘要： An integrated circuit device is disclosed. The device includes a first leadframe power supply bus and a second leadframe power supply bus that each have portions separate from and adjacent to one another that lie between a first plurality of leadfingers and a second plurality of leadfingers. An electronic device is connected to the first leadframe power supply bus and to the second leadframe power supply bus. Another electronic device can be connected to the first leadframe power supply bus and to the second leadframe bus. Exemplary of the electronic devices are a de-coupling capacitor and a capacitor for high frequency noise suppression. A semiconductor die is attached to the power supply busses. A substance encapsulates the components so that an integrated semiconductor chip is formed. A method of making an integrated circuit device is also disclosed.
摘要翻译：公开了一种集成电路器件。该装置包括第一引线框电源总线和第二引线框电源总线，每个引线框电源总线各自具有彼此分开并且彼此相邻的部分，其位于第一多个引线管和第二多个引线管之间。电子设备连接到第一引线框电源总线和第二引线框电源总线。另一电子设备可以连接到第一引线框电源总线和第二引线框总线。电子设备的示例是用于高频噪声抑制的去耦电容器和电容器。半导体管芯连接到电源总线上。一种物质封装组件，从而形成集成的半导体芯片。还公开了一种制造集成电路器件的方法。

8. 发明授权

US08437213B2 Characterization of bits in a functional memory 有权
标题翻译：功能存储器中的位的表征
公开(公告)号：US08437213B2
公开(公告)日：2013-05-07
申请号：US12347928
申请日：2008-12-31
申请人： Xiaowei Deng , Wah K. Loh , Theodore W. Houston
发明人： Xiaowei Deng , Wah K. Loh , Theodore W. Houston
IPC分类号： G11C5/14
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要： Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port.
摘要翻译：本公开的实施例提供了一种集成电路，其包括功能存储器和表征功能存储器中的存储器单元的组件或缺陷的方法。在一个实施例中，功能存储器包括具有外围源极和吸收电压供给端口的行和列周边单元，以行和列组织的存储器单元的阵列以及由提供对存储器单元的行访问的字线驱动器控制的字线的数组。此外，功能存储器还包括由直接位线访问电路控制的位线，其通过位线模拟访问端口和独立电压供应端口提供对存储器单元的直接位线访问。

9. 发明授权

US5115298A Packaged integrated circuit with encapsulated electronic devices 失效
标题翻译：封装的集成电路与封装的电子设备
公开(公告)号：US5115298A
公开(公告)日：1992-05-19
申请号：US470673
申请日：1990-01-26
申请人： Wah K. Loh
发明人： Wah K. Loh
IPC分类号： H01L23/50 , H01L23/495 , H01L23/58 , H01L23/62 , H01L25/00
CPC分类号： H01L23/49541 , H01L23/4951 , H01L23/49589 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/73215 , H01L2224/83101 , H01L24/48 , H01L2924/00014 , H01L2924/12035 , H01L2924/14 , H01L2924/1815 , H01L2924/19041 , H01L2924/30107
摘要： An integrated circuit device is disclosed. The device includes a first leadframe power supply bus and a second leadframe power supply bus that each have portions separate from and adjacent to one another that lie between a first plurality of leadfingers and a second plurality of leadfingers. An electronic device is connected to the first leadframe power supply bus and to the second leadframe power supply bus. Another electronic device can be connected to the first leadframe power supply bus and to the second leadframe bus. Exemplary of the electronic devices are a de-coupling capacitor and a capacitor for high frequency noise suppression. A semiconductor die is attached to the power supply busses. A substance encapsulates the components so that an integrated semiconductor chip is formed. A method of making an integrated circuit device is also disclosed.
摘要翻译：公开了一种集成电路器件。该装置包括第一引线框电源总线和第二引线框电源总线，每个引线框电源总线各自具有彼此分开并且彼此相邻的部分，其位于第一多个引线管和第二多个引线管之间。电子设备连接到第一引线框电源总线和第二引线框电源总线。另一电子设备可以连接到第一引线框电源总线和第二引线框总线。电子设备的示例是用于高频噪声抑制的去耦电容器和电容器。半导体管芯连接到电源总线上。一种物质封装组件，从而形成集成的半导体芯片。还公开了一种制造集成电路器件的方法。

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