专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07821816B2 Method for constructing Shmoo plots for SRAMs 有权
标题翻译：构建SRAM的Shmoo图的方法
公开(公告)号：US07821816B2
公开(公告)日：2010-10-26
申请号：US12401181
申请日：2009-03-10
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C11/00
CPC分类号： G11C29/44 , G11C11/41 , G11C29/023 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0405 , G11C2029/1202
摘要： A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.
摘要翻译：在每个测试电压测量点指定故障次数和故障类型的Shmoo图的准备方法。一种使用操作SRAM阵列电路来确定每个测试电压测量点可能发生的故障类型的方法。

2. 发明授权

US07499354B2 Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same 有权
标题翻译：用于测试具有与其他晶体管相同的有源区的晶体管的方法和用于实现其的测试电路
公开(公告)号：US07499354B2
公开(公告)日：2009-03-03
申请号：US11268974
申请日：2005-11-08
申请人： Theodore W. Houston , Xiaowei Deng , Tito Gelsomini
发明人： Theodore W. Houston , Xiaowei Deng , Tito Gelsomini
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G01R31/3008 , G11C11/41 , G11C29/50 , G11C2029/5006
摘要： The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors (110) located within a common active region, and biasing a terminal (135) between the pair (110) relative to gates (125, 155) of the pair (110) and terminals (130, 160) outlying the pair (110) to obtain a leakage current associated with the pair (110).
摘要翻译：本发明提供了一种用于测试位于与其它晶体管相同的有源区内的一个或多个功能分离的晶体管的电性能的方法，用于表征多个功能分离的晶体管中的至少一个的泄漏电流的方法，电路的公共有源区，以及用于测试位于公共有源区内的一个或多个功能分离的晶体管的测试结构。用于测试电性能的方法以及其它步骤包括提供位于公共有源区域内的一对功能分离的晶体管（110），并且相对于栅极（125,155）偏置所述对（110）之间的端子（135））和离开对（110）的端子（130,160）以获得与该对（110）相关联的泄漏电流。

3. 发明授权

US06922370B2 High performance SRAM device and method of powering-down the same 有权
标题翻译：高性能SRAM器件和断电方法相同
公开(公告)号：US06922370B2
公开(公告)日：2005-07-26
申请号：US10733485
申请日：2003-12-11
申请人： Xiaowei Deng , Hugh Mair , Theodore W. Houston , Luan Dang
发明人： Xiaowei Deng , Hugh Mair , Theodore W. Houston , Luan Dang
IPC分类号： G11C5/14 , G11C7/00 , G11C7/20 , G11C7/22 , G11C11/413 , G11C11/417
CPC分类号： G11C5/14 , G11C7/20 , G11C7/22 , G11C11/413 , G11C11/417 , G11C2207/2227
摘要： An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSB to the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.
摘要翻译： SRAM器件和SRAM器件掉电的方法。在一个实施例中，SRAM器件包括（1）耦合到SRAM阵列低电压源的SRAM阵列，其向SRAM器件提供低SRAM阵列电源电压V SB，并且（2）主列周边具有不具有SRAM头的主预充电电路的电路，通过位线耦合到SRAM阵列，并通过相关联的主列外围驱动电路耦合到睡眠模式控制器，该主列外围驱动电路被配置为在睡眠模式。

4. 发明授权

US06731533B2 Loadless 4T SRAM cell with PMOS drivers 有权
标题翻译：带PMOS驱动器的无负载4T SRAM单元
公开(公告)号：US06731533B2
公开(公告)日：2004-05-04
申请号：US09976983
申请日：2001-10-12
申请人： Xiaowei Deng , Theodore W. Houston
发明人： Xiaowei Deng , Theodore W. Houston
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： The instant invention comprises a memory cell with PMOS drive transistors (170, 180) and NMOS pass transistors (150, 160). A NMOS transistor is connected between a storage node (230) and a bitline (200). The NMOS transistor is gated by the wordline (190). A PMOS drive transistor (180) is connected between the storage node (230) and a supply voltage (255).
摘要翻译：本发明包括具有PMOS驱动晶体管（170,180）和NMOS传输晶体管（150,160）的存储单元。 NMOS晶体管连接在存储节点（230）和位线（200）之间。 NMOS晶体管由字线（190）选通。 PMOS驱动晶体管（180）连接在存储节点（230）和电源电压（255）之间。

5. 发明授权

US06573549B1 Dynamic threshold voltage 6T SRAM cell 有权
标题翻译：动态阈值电压6T SRAM单元
公开(公告)号：US06573549B1
公开(公告)日：2003-06-03
申请号：US10177773
申请日：2002-06-21
申请人： Xiaowei Deng , Theodore W. Houston
发明人： Xiaowei Deng , Theodore W. Houston
IPC分类号： H01L2708
CPC分类号： H01L27/12 , H01L27/1108
摘要： An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor (130 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor.
摘要翻译：本发明的实施例是一种存储器件，包括：存储单元，包括：第一晶体管（图1的108），其具有控制电极，电流路径和电连接到第一晶体管; 和具有电连接到第二晶体管的控制电极和第一晶体管的电流通路的控制电极，电流路径和背栅极/主体连接的第二晶体管（130），第一晶体管的电流通路第二晶体管连接到第一晶体管的背栅极/主体连接; 输入/输出导体; 以及将存储单元耦合到输入/输出导体的传输晶体管。

6. 发明授权

US08379467B2 Structure and methods for measuring margins in an SRAM bit 有权
标题翻译：用于测量SRAM位中边缘的结构和方法
公开(公告)号：US08379467B2
公开(公告)日：2013-02-19
申请号：US13043229
申请日：2011-03-08
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/413 , G11C11/419 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： Integrated circuit for performing test operation of static RAM bit and for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, the integrated circuit has a built-in self-test circuit for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.
摘要翻译：集成电路，用于执行静态RAM位的测试操作，并用于测量SRAM位的读取余量，写入余量和稳定裕度，其中包含SRAM阵列架构和电路设计的操作电路。此外，集成电路还具有内置的自检电路，用于测量SRAM的读取余量，写入余量和稳定裕度，排除了SRAM阵列结构和电路设计的影响。

7. 发明授权

US08064279B2 Structure and method for screening SRAMS 有权
标题翻译：筛选SRAMS的结构和方法
公开(公告)号：US08064279B2
公开(公告)日：2011-11-22
申请号：US12502879
申请日：2009-07-14
申请人： Theodore W. Houston , Xiaowei Deng
发明人： Theodore W. Houston , Xiaowei Deng
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12 , G11C2029/1202
摘要： An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.
摘要翻译：包含SRAM的集成电路，其提供开关以在屏蔽期间将SRAM字线电压与SRAM阵列电压分离，并且在SRAM位筛选测试的一部分期间还提供不同的字线和阵列电压。一种用于在SRAM阵列中筛选SRAM位的方法，其中在屏蔽测试的一部分期间字线电压不同于阵列电压。

8. 发明授权

US07027346B2 Bit line control for low power in standby 有权
标题翻译：位线控制为低功耗待机
公开(公告)号：US07027346B2
公开(公告)日：2006-04-11
申请号：US10337069
申请日：2003-01-06
申请人： Theodore W. Houston , Xiaowei Deng
发明人： Theodore W. Houston , Xiaowei Deng
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/417 , G11C2207/2227
摘要： The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.
摘要翻译：本发明实现了在待机期间控制位线电压（BLB / BLB）的SRAM单元（20,30）的实施例的技术优点，例如允许位线浮动允许位线电压通过平衡泄漏电流通过位线的最小泄漏。有利地，控制器（22,32）还控制电源电压Vdd，Vss和n阱（V N nwell）电压。控制器在待机模式下降低电源电压Vdd与电压Vss之间的电压差。在一个实施例中，位线可以被连接到参考电压Vss，并且可以引入时间延迟以减少在切换中使用比所保存的更多电荷的可能性。

9. 发明申请

US20110158018A1 Structure and Methods for Measuring Margins in an SRAM Bit 有权
标题翻译： SRAM位测量结构和方法
公开(公告)号：US20110158018A1
公开(公告)日：2011-06-30
申请号：US13043229
申请日：2011-03-08
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C29/12
CPC分类号： G11C8/08 , G11C11/413 , G11C11/419 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.
摘要翻译：使用包括SRAM阵列结构和电路设计效果的操作电路来测量SRAM位的读余量，写余量和稳定裕度的方法。另外，用于测量SRAM的读取余量，写入余量和稳定裕度的方法，排除了SRAM阵列架构和电路设计的影响。

10. 发明申请

US20110013470A1 Structure and Method for Screening SRAMS 有权
标题翻译：筛选SRAMS的结构和方法
公开(公告)号：US20110013470A1
公开(公告)日：2011-01-20
申请号：US12502879
申请日：2009-07-14
申请人： Theodore W. Houston , Xiaowei Deng
发明人： Theodore W. Houston , Xiaowei Deng
IPC分类号： G11C29/00 , G11C8/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12 , G11C2029/1202
摘要： An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.
摘要翻译：包含SRAM的集成电路，其提供开关以在屏蔽期间将SRAM字线电压与SRAM阵列电压分离，并且在SRAM位筛选测试的一部分期间还提供不同的字线和阵列电压。一种用于在SRAM阵列中筛选SRAM位的方法，其中在屏蔽测试的一部分期间字线电压不同于阵列电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式