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71. 发明申请

US20090190405A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090190405A1
公开(公告)日：2009-07-30
申请号：US12350398
申请日：2009-01-08
申请人： Naoya Tokiwa , Masanobu Shirakawa
发明人： Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C8/00 , G11C16/06
CPC分类号： G11C29/12 , G11C16/04 , G11C16/10 , G11C29/1201 , G11C2029/2602
摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.
摘要翻译：非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置寄存器电路对应于多个地址。

72. 发明授权

US07463515B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07463515B2
公开(公告)日：2008-12-09
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/26
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

73. 发明授权

US07369457B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07369457B2
公开(公告)日：2008-05-06
申请号：US11767025
申请日：2007-06-22
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32
摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.
摘要翻译：半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元; 被配置为耦合到所述存储单元阵列的读出放大器电路; 设置在读出放大器电路和数据输入/输出端口之间的数据传输电路; 控制信号生成电路，被配置为基于外部提供的参考时钟信号生成多个控制信号，所述控制信号用于控制读出放大器电路的数据输入和输出以及数据传送电路中的数据传送定时; 以及内部时钟信号生成电路，被配置为基于用于作为控制信号的基础的参考时钟信号产生内部时钟信号，内部时钟信号具有与参考时钟信号相同的时钟周期和不具有恒定占空比的内部时钟信号关于参考时钟信号的占空比。

74. 发明申请

US20070297236A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070297236A1
公开(公告)日：2007-12-27
申请号：US11754531
申请日：2007-05-29
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/0483
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data storage circuit configured to store data simultaneously read from or written into the memory cell array, the data constituting a collective processing unit; and a data state judgment circuit configured to sequentially judge the data states of multiple divided areas, which are obtained by dividing the collective processing unit.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 数据存储电路，被配置为存储同时从存储单元阵列读取或写入存储单元阵列的数据，所述数据构成集合处理单元; 以及数据状态判断电路，被配置为顺序地判断通过分割集体处理单元获得的多个分割区域的数据状态。

75. 发明申请

US20070147144A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20070147144A1
公开(公告)日：2007-06-28
申请号：US11616112
申请日：2006-12-26
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C16/06 , G11C11/34 , G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C16/0483 , G11C29/82
摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence.
摘要翻译：半导体集成电路装置包括具有多个块的存储单元阵列，存储单元，块替换信息寄存器组和坏块标志寄存器组。存储单元包括可以注册块替换信息的块替换信息登记区域和可以注册坏块信息的坏块信息登记区域。根据在引导顺序期间从存储单元读出的块替换信息来设置块替换信息寄存器组，并且根据读取的块替换信息和坏块信息两者来设置坏块标志寄存器组在引导顺序期间从存储单元出来。

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