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71. 发明授权

US5635423A Simplified dual damascene process for multi-level metallization and interconnection structure 失效
标题翻译：用于多层次金属化和互连结构的简化双镶嵌工艺
公开(公告)号：US5635423A
公开(公告)日：1997-06-03
申请号：US320516
申请日：1994-10-11
申请人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
发明人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7681 , H01L21/76807 , H01L21/76813
摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
摘要翻译：通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。沟槽和通孔然后同时填充导电材料。

72. 发明授权

US08580660B2 Double and triple gate MOSFET devices and methods for making same 有权
标题翻译：双栅极和三栅极MOSFET器件及其制造方法
公开(公告)号：US08580660B2
公开(公告)日：2013-11-12
申请号：US13523603
申请日：2012-06-14
申请人： Ming-Ren Lin , Judy Xilin An , Zoran Krivokapic , Cyrus E. Tabery , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Judy Xilin An , Zoran Krivokapic , Cyrus E. Tabery , Haihong Wang , Bin Yu
IPC分类号： H01L29/72
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/66818
摘要： A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.
摘要翻译：双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。第一个门形成在鳍的顶部。第二个门围绕翅片和第一个门。在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。第一个门形成在鳍的顶部。第二个门形成在翅片附近。第三栅极形成在翅片附近并与第二栅极相对。

73. 发明申请

US20110263094A1 METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION 有权
标题翻译：形成具有热分解的微结构半导体器件的方法
公开(公告)号：US20110263094A1
公开(公告)日：2011-10-27
申请号：US13176614
申请日：2011-07-05
申请人： Ming-ren LIN , Zoran KRIVOKAPIC , Witek MASZARA
发明人： Ming-ren LIN , Zoran KRIVOKAPIC , Witek MASZARA
IPC分类号： H01L21/76
CPC分类号： H01L21/823431 , H01L21/76232 , H01L29/66795 , H01L29/66818 , H01L29/7851
摘要： A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner.
摘要翻译：提供了诸如FinFET器件结构的半导体器件结构的制造方法。该方法开始于提供包括体半导体材料的衬底，由体半导体材料形成的第一导电鳍结构以及由体半导体材料形成的第二导电鳍结构。第一导电鳍结构和第二导电鳍结构被间隙分开。接下来，间隔件形成在间隙中并且与第一导电翅片结构和第二导电翅片结构相邻。此后，蚀刻步骤使用间隔物作为蚀刻掩模来蚀刻体半导体材料，以在体半导体材料中形成隔离沟槽。绝缘材料形成在隔离沟槽中，在间隔物之上，在第一导电鳍结构之上，并在第二导电鳍结构之上。此后，介电材料的至少一部分和至少一部分间隔物被蚀刻掉以露出第一导电鳍结构的上部和第二导电翅片结构的上部，同时将介电材料保留在隔离沟按照这些步骤，以常规方式完成装置的制造。

74. 发明授权

US07235436B1 Method for doping structures in FinFET devices 有权
标题翻译： FinFET器件掺杂结构的方法
公开(公告)号：US07235436B1
公开(公告)日：2007-06-26
申请号：US10614051
申请日：2003-07-08
申请人： Ming-Ren Lin , Zoran Krivokapic , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Zoran Krivokapic , Haihong Wang , Bin Yu
IPC分类号： H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method for doping fin structures in FinFET devices includes forming a first glass layer on the fin structure of a first area and a second area. The method further includes removing the first glass layer from the second area, forming a second glass layer on the fin structure of the first area and the second area, and annealing the first area and the second area to dope the fin structures.
摘要翻译：在FinFET器件中掺杂鳍结构的方法包括在第一区域和第二区域的鳍结构上形成第一玻璃层。该方法还包括从第二区域去除第一玻璃层，在第一区域和第二区域的翅片结构上形成第二玻璃层，并退火第一区域和第二区域以掺杂翅片结构。

75. 发明授权

US07196374B1 Doped structure for FinFET devices 有权
标题翻译： FinFET器件的掺杂结构
公开(公告)号：US07196374B1
公开(公告)日：2007-03-27
申请号：US10653274
申请日：2003-09-03
申请人： Ming-Ren Lin , Bin Yu
发明人： Ming-Ren Lin , Bin Yu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/78687
摘要： A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.
摘要翻译：半导体器件包括衬底和衬底上的绝缘层。半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构。

76. 发明授权

US07001837B2 Semiconductor with tensile strained substrate and method of making the same 有权
标题翻译：具有拉伸应变衬底的半导体及其制造方法
公开(公告)号：US07001837B2
公开(公告)日：2006-02-21
申请号：US10346617
申请日：2003-01-17
申请人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
发明人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
IPC分类号： H01L21/4763
CPC分类号： H01L29/7843 , H01L29/1054 , H01L2924/0002 , Y10S257/90 , Y10S438/933 , H01L2924/00
摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.
摘要翻译：示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

77. 发明授权

US06958264B1 Scribe lane for gettering of contaminants on SOI wafers and gettering method 有权
标题翻译：用于吸收SOI晶片上的污染物的划痕通道和吸气方法
公开(公告)号：US06958264B1
公开(公告)日：2005-10-25
申请号：US09824933
申请日：2001-04-03
申请人： Ming-Ren Lin
发明人： Ming-Ren Lin
IPC分类号： H01L21/322 , H01L21/335 , H01L21/8232
CPC分类号： H01L21/3221
摘要： A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites. A silicon-on-insulator semiconductor wafer including a silicon active layer; a plurality of die pads formed in the silicon active layer; at least one scribe lane between and separating adjacent die pads; and at least one gettering plug in the at least one scribe lane, wherein the at least one gettering plug extends through the silicon active layer and the gettering plug comprises a doped fill material having a plurality of gettering sites.
摘要翻译：一种在绝缘体上硅晶片上制造半导体器件的方法，其包括其上形成有至少两个管芯焊盘的硅有源层，所述至少两个管芯焊盘由至少一个划线通道隔开，包括至少形成通过所述至少一个划线中的所述硅有源层的一个空腔; 在每个所述空腔中形成至少一个吸气塞，每个所述吸气塞包括含有多个吸气位点的掺杂填料; 并且使所述晶片经受条件以将至少一种杂质吸入所述多个吸气部位。包括硅有源层的绝缘体上硅半导体晶片; 形成在所述硅有源层中的多个管芯焊盘; 在相邻的管芯焊盘之间和分离相邻的管芯焊盘之间的至少一个划线; 以及在所述至少一个划线中的至少一个吸气塞，其中所述至少一个吸气塞延伸穿过所述硅有源层，并且所述吸气塞包括具有多个吸气位点的掺杂填料。

78. 发明授权

US06812119B1 Narrow fins by oxidation in double-gate finfet 有权
标题翻译：狭窄的翅片通过氧化在双门finfet
公开(公告)号：US06812119B1
公开(公告)日：2004-11-02
申请号：US10614052
申请日：2003-07-08
申请人： Shibly S. Ahmed , Ming-Ren Lin , Haihong Wang , Bin Yu
发明人： Shibly S. Ahmed , Ming-Ren Lin , Haihong Wang , Bin Yu
IPC分类号： H01L213205
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
摘要翻译：一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。该方法还包括在每个双盖的侧面上形成间隔物，并在双重帽下面的第一半导体材料层中形成双翅片。该方法还包括使双翅片变薄以产生窄的双翅片。

79. 发明授权

US06790782B1 Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal 有权
标题翻译：包括高K栅极电介质的晶体管栅极的制造工艺，其具有原位抗蚀剂修整，栅极蚀刻和高K电介质去除
公开(公告)号：US06790782B1
公开(公告)日：2004-09-14
申请号：US10157450
申请日：2002-05-29
申请人： Chih-Yuh Yang , Cyrus E. Tabery , Ming-Ren Lin
发明人： Chih-Yuh Yang , Cyrus E. Tabery , Ming-Ren Lin
IPC分类号： H01L21302
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/28273 , H01L29/517
摘要： The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.
摘要翻译：本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。该方法提供了处理步骤，其包括在单个蚀刻室中有效执行的栅极图案修整，栅极堆叠蚀刻和去除高K电介质的暴露区域。因此，降低了处理复杂性和处理成本，同时提高了吞吐量和整体处理效率。该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层，以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。在高K电介质层上方制造多晶硅层。在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。

80. 发明授权

US06787864B2 Mosfets incorporating nickel germanosilicided gate and methods for their formation 有权
公开(公告)号：US06787864B2
公开(公告)日：2004-09-07
申请号：US10335492
申请日：2002-12-31
申请人： Eric N. Paton , Qi Xiang , Paul R. Besser , Ming-Ren Lin , Minh V. Ngo , Haihong Wang
发明人： Eric N. Paton , Qi Xiang , Paul R. Besser , Ming-Ren Lin , Minh V. Ngo , Haihong Wang
IPC分类号： H01L2972
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/1054 , H01L29/4908 , H01L29/66477 , H01L29/665 , H01L29/66795 , H01L2029/7858
摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

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