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71. 发明授权

US08537617B2 Source side asymmetrical precharge programming scheme 有权
标题翻译：源极不对称预充电编程方案
公开(公告)号：US08537617B2
公开(公告)日：2013-09-17
申请号：US13365913
申请日：2012-02-03
申请人： Jin-Ki Kim , Hong Beom Pyeon
发明人： Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10
摘要： A method for programming a NAND flash string. In the present method, wordlines are driven to a first pass voltage for coupling a string precharge voltage provided by a source line to the memory cells, where the string precharge voltage is greater than the first pass voltage. With the exception a first wordline corresponding to a first memory cell adjacent to a selected memory cell, all the other wordlines are driven to a second pass voltage greater than the first pass voltage. The first memory cell is positioned between the selected memory cell and a string select device. A second wordline corresponding to a second memory cell adjacent to the selected memory cell is driven to a first supply voltage for turning off the second memory cell. A third wordline corresponding to the selected memory cell is driven to a programming voltage greater than the second pass voltage. A bitline is then coupled to the selected memory cell.
摘要翻译：一种用于编程NAND闪存串的方法。在本方法中，字线被驱动到第一通过电压，用于将由源极线提供的串预充电电压耦合到存储器单元，其中串预充电电压大于第一通过电压。除了对应于与所选择的存储器单元相邻的第一存储单元的第一字线外，所有其它字线被驱动到大于第一通过电压的第二通过电压。第一存储器单元位于所选存储单元和字符串选择器件之间。对应于与所选存储单元相邻的第二存储单元的第二字线被驱动到用于关闭第二存储单元的第一电源电压。对应于所选存储单元的第三字线被驱动到大于第二通过电压的编程电压。然后将位线耦合到所选择的存储器单元。

72. 发明授权

US08407395B2 Scalable memory system 失效
标题翻译：可扩展内存系统
公开(公告)号：US08407395B2
公开(公告)日：2013-03-26
申请号：US11843440
申请日：2007-08-22
申请人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon , Steven Przybylski
发明人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon , Steven Przybylski
IPC分类号： G06F12/00
CPC分类号： G11C7/1042 , G06F12/0623 , G06F13/1694 , G06F13/4256 , G11C7/10 , G11C7/22 , G11C16/06 , G11C16/10 , G11C2216/30 , Y02D10/14 , Y02D10/151
摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
摘要翻译：存储器系统架构具有串行连接的存储器件。内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

73. 发明授权

US08407371B2 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 有权
公开(公告)号：US08407371B2
公开(公告)日：2013-03-26
申请号：US13077168
申请日：2011-03-31
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： G06F3/00
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

74. 发明授权

US08399973B2 Data storage and stackable configurations 有权
标题翻译：数据存储和可堆叠配置
公开(公告)号：US08399973B2
公开(公告)日：2013-03-19
申请号：US12168354
申请日：2008-07-07
申请人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
发明人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/01015 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00015
摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices.
摘要翻译：第一存储器件和第二存储器件具有相同的输入/输出布局配置。为了形成堆叠，第二存储器件被固定到第一存储器件。为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。基于输出和来自堆叠中的一个存储器设备的输入之间的链接，存储器件堆可以包括通过其存储器件便于一个或多个串联连接配置的路径。

75. 发明授权

US08379450B2 Non-volatile memory device having configurable page size 有权
公开(公告)号：US08379450B2
公开(公告)日：2013-02-19
申请号：US13276856
申请日：2011-10-19
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

76. 发明申请

US20130016557A1 SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STRUCTURE 审中-公开
标题翻译：具有三维结构的半导体存储器件
公开(公告)号：US20130016557A1
公开(公告)日：2013-01-17
申请号：US13636574
申请日：2011-04-04
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： H01L45/00 , H01L21/8239 , G11C11/34
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A three-dimensional memory device includes a stack of semiconductor layers. Phase change memory (PCM) cell arrays are formed on each layer. Each PCM cell includes a variable resistor as storage element, the resistance of which varies. On one layer, formed is peripheral circuitry which includes row and column decoders, sense amplifiers and global column selectors to control operation of the memory. Local bit lines and worldliness are connected to the memory cells. The global column selectors select global bitlines to be connected to local bit lines. The row decoder selects wordlines. Applied current flows through the memory cell connected to the selected local bitline and wordline. In write operation, set current or reset current is applied and the variable resistor of the selected PCM cell stores “data”. In read operation, read current is applied and voltage developed across the variable resistor is compared to a reference voltage to provide as read data.
摘要翻译：三维存储器件包括一叠半导体层。在每个层上形成相变存储器（PCM）单元阵列。每个PCM单元包括可变电阻器作为存储元件，其电阻变化。形成的一个层是包括行和列解码器，读出放大器和全局列选择器以控制存储器的操作的外围电路。本地位线和全局连接到存储单元。全局列选择器选择要连接到本地位线的全局位线。行解码器选择字线。施加的电流流过连接到选定的本地位线和字线的存储单元。在写操作中，设置电流或复位电流，所选PCM单元的可变电阻存储数据。在读操作中，读取电流并将可变电阻器上产生的电压与参考电压进行比较，以提供读数据。

77. 发明授权

US08351265B2 Power supplies in flash memory devices and systems 有权
标题翻译：闪存设备和系统中的电源
公开(公告)号：US08351265B2
公开(公告)日：2013-01-08
申请号：US13249744
申请日：2011-09-30
申请人： Hong Beom Pyeon , Jin-Ki Kim
发明人： Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C5/145 , G11C5/147 , H02M3/073
摘要： Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level.
摘要翻译：公开了闪存设备中的电源。闪存器件的第一部分包括用于存储数据的非易失性存储器。闪存器件的第二部分至少包括第一和第二泵浦电路。第一泵送电路接收第一电压，并且在第一泵送电路的输出处产生高于第一电压电平的第二电压电平的第二电压。第二泵浦电路具有耦合到第一泵浦电路输出的输入端，用于协同地采用第一泵浦电路从大于第一电压的电压泵浦，以产生高于第二电压电平的第三电压电平的第三电压。

78. 发明申请

US20130003470A1 INDEPENDENT LINK AND BANK SELECTION 有权
标题翻译：独立链接和银行选择
公开(公告)号：US20130003470A1
公开(公告)日：2013-01-03
申请号：US13608605
申请日：2012-09-10
申请人： HONG BEOM PYEON , HAKJUNE OH , JIN-KI KIM
发明人： HONG BEOM PYEON , HAKJUNE OH , JIN-KI KIM
IPC分类号： G11C7/00
CPC分类号： G06F13/4022 , G11C7/1048 , G11C7/18 , G11C11/408
摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
摘要翻译：提供了具有多个存储体和多个链接控制器的存储器系统。对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问通过相同的链路控制器到多个银行。

79. 发明授权

US08339826B2 Stacked semiconductor devices including a master device 有权
标题翻译：堆叠的半导体器件包括主器件
公开(公告)号：US08339826B2
公开(公告)日：2012-12-25
申请号：US13005774
申请日：2011-01-13
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , G11C5/02 , G11C5/06 , G11C16/30 , H01L21/50 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
摘要翻译：公开了一种包括非易失性存储器件的堆叠。堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

80. 发明申请

US20120320693A1 DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：双功能兼容的非易失性存储器件
公开(公告)号：US20120320693A1
公开(公告)日：2012-12-20
申请号：US13592953
申请日：2012-08-23
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C7/00
CPC分类号： G11C16/06 , G11C5/14 , G11C5/143 , G11C7/20 , G11C16/20
摘要： A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
摘要翻译：兼容异步操作和同步串行操作的双功能存储器件架构。双功能存储设备架构包括具有两个不同功能分配的一组物理端口。存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

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