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1. 发明授权

US09183892B2 Data storage and stackable chip configurations 有权
标题翻译：数据存储和堆叠芯片配置
公开(公告)号：US09183892B2
公开(公告)日：2015-11-10
申请号：US13765059
申请日：2013-02-12
申请人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
发明人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： H01L23/02 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40 , G11C5/06 , G11C5/02 , G11C5/04 , H01L25/065
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/01015 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00015
摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.
摘要翻译：第一存储器件和第二存储器件具有相同的输入/输出布局配置。为了形成堆叠，第二存储器件被固定到第一存储器件。为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。基于输出之间的链路和堆叠中的一个存储设备到另一存储设备的输入，存储器设备堆叠可以包括便于通过存储器设备的一个或多个串联连接配置的路径。

2. 发明授权

US08891322B2 Memory system with a layer comprising a dedicated redundancy area 有权
标题翻译：具有包括专用冗余区域的层的存储器系统
公开(公告)号：US08891322B2
公开(公告)日：2014-11-18
申请号：US13621486
申请日：2012-09-17
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： G11C29/00 , G11C29/44 , G11C29/12
CPC分类号： G11C29/785 , G11C29/44 , G11C2029/1206 , G11C2029/4402
摘要： Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.
摘要翻译：公开了可以包括包括第一冗余存储器元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。此外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝熔断控制提供信息，其分配第一冗余存储器的一部分元件，以通过在第一层熔丝盒和第二层熔丝盒中吹入元件来为第二层存储元件的故障部分提供冗余。

3. 发明授权

US08781053B2 Clock reproducing and timing method in a system having a plurality of devices 有权
标题翻译：具有多个装置的系统中的时钟再现和定时方法
公开(公告)号：US08781053B2
公开(公告)日：2014-07-15
申请号：US12168091
申请日：2008-07-04
申请人： Hong Beom Pyeon , Peter Gillingham
发明人： Hong Beom Pyeon , Peter Gillingham
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , G06F13/1689 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06562 , Y02D10/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.
摘要翻译：系统包括存储器控制器和串联连接的多个半导体器件。每个设备具有用于存储数据的存储器核心。存储器控制器提供用于同步器件的操作的时钟信号。每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。数据传输与再现的时钟信号中的至少一个同步。在禁用PLL的器件中，数据传输与输入时钟信号同步。使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。设备可以分组。一组的器件可以由多个芯片封装构成。

4. 发明授权

US08700818B2 Packet based ID generation for serially interconnected devices 有权
标题翻译：用于串行互连设备的基于分组的ID生成
公开(公告)号：US08700818B2
公开(公告)日：2014-04-15
申请号：US11529293
申请日：2006-09-29
申请人： Hong Beom Pyeon , HakJune Oh
发明人： Hong Beom Pyeon , HakJune Oh
IPC分类号： G06F3/00 , G06F1/12
CPC分类号： G06F1/12 , G06F1/04 , G11C5/00 , G11C5/066 , G11C7/20
摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
摘要翻译：各种存储器件（例如，DRAM，闪存）串联连接。存储器件需要它们的标识符（ID）。每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。命令数据和先前生成的ID数据被同步地注册。注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。计算是一个加法或减法。通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。响应于解释的ID和时钟来控制时钟延迟。根据受控时钟延迟，以分组为基础提供新的ID。在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

5. 发明授权

US08675410B2 Hierarchical common source line structure in NAND flash memory 有权
标题翻译： NAND闪存中的分层公共源线结构
公开(公告)号：US08675410B2
公开(公告)日：2014-03-18
申请号：US13481888
申请日：2012-05-28
申请人： Hong-Beom Pyeon , Jin-Ki Kim
发明人： Hong-Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
摘要翻译：通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。对于源行页面编程，分发线可以称为全局公用源线（GCSL）。在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

6. 发明授权

US08664748B2 Package-level integrated circuit connection without top metal pads or bonding wire 失效
标题翻译：封装级集成电路连接，无顶部金属焊盘或接合线
公开(公告)号：US08664748B2
公开(公告)日：2014-03-04
申请号：US12701122
申请日：2010-02-05
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： H01L23/544 , H01L21/78
CPC分类号： H01L21/82 , H01L23/49805 , H01L24/05 , H01L24/24 , H01L24/37 , H01L24/40 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/05599 , H01L2224/24145 , H01L2224/371 , H01L2224/37599 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/84
摘要： An integrated circuit apparatus is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.
摘要翻译：集成电路设备具有封装级连接性，其内部电子电路与其封装衬底上的接触点之间，而不需要顶部金属焊盘或接合线。

7. 发明授权

US08526227B2 Phase change memory word line driver 有权
标题翻译：相变存储器字线驱动器
公开(公告)号：US08526227B2
公开(公告)日：2013-09-03
申请号：US13110399
申请日：2011-05-18
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C2013/0071
摘要： A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.
摘要翻译：一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

8. 发明申请

US20130182485A1 Data Storage and Stackable Configurations 有权
标题翻译：数据存储和可堆叠配置
公开(公告)号：US20130182485A1
公开(公告)日：2013-07-18
申请号：US13765059
申请日：2013-02-12
申请人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
发明人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/01015 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00015
摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.
摘要翻译：第一存储器件和第二存储器件具有相同的输入/输出布局配置。为了形成堆栈，第二存储器件被固定到第一存储器件。为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。基于输出之间的链路和堆叠中的一个存储设备到另一存储设备的输入，存储器设备堆叠可以包括便于通过存储器设备的一个或多个串联连接配置的路径。

9. 发明授权

US08383514B2 Method for stacking serially-connected integrated circuits and multi-chip device made from same 有权
标题翻译：串联集成电路的堆叠方法和由其制成的多芯片器件
公开(公告)号：US08383514B2
公开(公告)日：2013-02-26
申请号：US13046197
申请日：2011-03-11
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： H01L23/538 , H01L23/48 , H01L23/485 , H01L21/768
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/066 , G11C16/06 , G11C19/00 , H01L21/76898 , H01L24/06 , H01L2224/05554 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/14 , H01L2924/00
摘要： A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.
摘要翻译：提供了堆叠多个基本上相同的芯片以产生该装置的多芯片装置和方法。多芯片器件或电路包括至少一个穿芯片通孔，其通过提供来自至少两个芯片的信号焊盘之间的并联连接以及至少一个穿芯片通孔，以提供从信号焊盘处的串联或菊花链连接至少两块芯片。公共连接信号焊盘相对于重复的公共信号焊盘对称地布置在芯片的中心线上。输入信号焊盘相对于相应的输出信号焊盘对称地设置在芯片的中心线周围。堆叠中的芯片是基本上相同的芯片的交替翻转版本，以提供这种布置。当堆叠超过两个芯片时，至少有一个串行连接提供在堆叠和翻转芯片的信号焊盘之间。

10. 发明申请

US20120320674A1 MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION 有权
标题翻译：具有双重功能的多级电池访问缓冲器
公开(公告)号：US20120320674A1
公开(公告)日：2012-12-20
申请号：US13595466
申请日：2012-08-27
申请人： Hong Beom PYEON
发明人： Hong Beom PYEON
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5642 , G11C2211/5647
摘要： An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.
摘要翻译：提供了使用两级MLC（多级单元）操作的诸如页面缓冲器的访问缓冲器，用于写入诸如Flash的非易失性存储器。访问缓冲器具有用于临时存储要写入的数据的第一锁存器。提供第二锁存器用于从作为两级写入操作的一部分的数据从存储器读取数据。第二个锁存器具有从存储器读取时参与锁存功能的反相器。相同的反相器用于产生正被写入第一锁存器的输入信号的补码，结果是使用双端输入来写入第一锁存器。

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