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61. 发明申请

US20020068371A1 Temperature measuring method and apparatus in semiconductor processing apparatus, and semiconductor processing method and apparatus 失效
标题翻译：半导体处理装置中的温度测量方法和装置以及半导体处理方法和装置
公开(公告)号：US20020068371A1
公开(公告)日：2002-06-06
申请号：US09995769
申请日：2001-11-29
申请人： TOKYO ELECTRON LIMITED
发明人： Mo Yun
IPC分类号： H01L021/66 , G01R031/26 , H01L021/26 , H01L021/324 , H01L021/42 , H01L021/477
CPC分类号： H01L22/26 , G01K7/42 , H01L21/67248 , H01L2924/0002 , H01L2924/00
摘要： A temperature measuring method for a target substrate to be thermally processed in a semiconductor processing apparatus under a predetermined process condition is provided. This method includes the steps of detecting a heat flux supplied from at least part of the target substrate and detecting a temperature of a sensor by using the sensor facing the target substrate, and calculating a temperature of the target substrate from a parameter, including a thermal resistance between the sensor and the target substrate under the predetermined process condition, the detected heat flux, and the temperature of the sensor. The sensor is arranged opposite to heating means, through the target substrate, which heats the target substrate. The parameter may be obtained in advance by calibration.
摘要翻译：提供了一种在预定工艺条件下在半导体处理装置中进行热处理的目标基板的温度测量方法。该方法包括以下步骤：检测从目标基板的至少一部分供给的热通量，并通过使用面向目标基板的传感器检测传感器的温度，并根据包括热量的参数计算目标基板的温度在预定工艺条件下传感器和目标衬底之间的电阻，检测到的热通量和传感器的温度。传感器与加热装置相对设置，通过加热目标基板的目标基板。该参数可以通过校准提前获得。

62. 发明申请

US20020058387A1 SOI annealing method and SOI manufacturing method 失效
标题翻译： SOI退火方法和SOI制造方法
公开(公告)号：US20020058387A1
公开(公告)日：2002-05-16
申请号：US09961420
申请日：2001-09-25
发明人： Masataka Ito
IPC分类号： H01L021/336 , H01L021/26 , H01L021/324
CPC分类号： H01L21/76259
摘要： The HF defect density in an SOI is reduced. An SOI having a thickness of 200 nm or less is annealed in an inert atmosphere at a temperature between the eutectic temperature (e.g., 966null C.) of a semiconductor metal compound (e.g., nickel silicide) formed from a metal and the semiconductor material of the crystal semiconductor of the SOI (inclusive) and the melting point of the semiconductor material (inclusive).
摘要翻译： SOI中的HF缺陷密度减小。厚度为200nm以下的SOI在由金属形成的半导体金属化合物（例如，硅化镍）的共晶温度（例如966℃）和半导体材料之间的温度下在惰性气氛中退火的SOI（包含）晶体半导体和半导体材料的熔点（含）。

63. 发明申请

US20010053617A1 Transportation method for a semiconductor device and transportation route selection method for a semiconductor device 有权
标题翻译：半导体装置的运送方法以及半导体装置的运送路径选择方法
公开(公告)号：US20010053617A1
公开(公告)日：2001-12-20
申请号：US09800010
申请日：2001-03-06
发明人： Hiroo Shoji
IPC分类号： H01L021/26 , H01L021/324 , H01L021/42 , H01L021/477 , B65G049/07
CPC分类号： G05B19/41865 , G05B2219/31281 , G05B2219/32015 , G05B2219/32187 , G05B2219/32188 , Y02P90/20 , Y02P90/22 , Y02P90/28 , Y10S414/135
摘要： The occurrence of defects of a semiconductor device at the time of transportation is prevented by the present invention relates to a transportation method for a semiconductor device which uses, for transportation of a semiconductor device from the departure point to the arrival point, the transportation route B1nullB2 wherein the cosmic ray concentration is the smallest among a plurality of transportation routes A and B1nullB2 from the departure point to the arrival point. In addition, the invention also relates to a transportation route selection method for a semiconductor device comprising the step of inputting a departure point and an arrival point for the transportation for a semiconductor device, the step of calculating a plurality of transportation routes A and B1nullB2 from the departure point to the arrival point, the step of calculating the cosmic ray concentration in each of the plurality of transportation routes A and B1nullB2 and the step of selecting the transportation route wherein the cosmic ray concentration is the smallest among the plurality of transportation routes A and B1nullB2.
摘要翻译：本发明涉及半导体装置的运输方法，该半导体装置用于从出发地到达点运输半导体装置的运输路线B1 + B2，其中宇宙射线浓度在从出发点到到达点的多个运输路线A和B1 + B2中最小。此外，本发明还涉及一种半导体装置的运输路线选择方法，包括输入半导体装置的运送的出发地点和到达点的步骤，计算多个运送路线A，B1 + 从出发点到到达点的B2，计算多个交通路线A和B1 + B2中的每一个中的宇宙射线浓度的步骤以及选择多个运送路线中的宇宙射线浓度最小的运送路线的步骤的交通路线A和B1 + B2。

64. 发明申请

US20010041461A1 PROCESS FOR FORMING HIGH VOLTAGE JUNCTION TERMINATION EXTENSION OXIDE 审中-公开
标题翻译：用于形成高电压连接终止氧化物的方法
公开(公告)号：US20010041461A1
公开(公告)日：2001-11-15
申请号：US09167177
申请日：1998-10-06
发明人： RODNEY S. RIDLEY , JASON R. TROST , RAYMOND J. WEBB
IPC分类号： H01L021/31 , H01L021/469 , H01L021/26 , H01L021/336
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/0332 , H01L21/0337 , H01L21/2253 , H01L21/266 , H01L21/31662 , H01L29/0619
摘要： A process for forming a junction termination extension (JTE) oxide having reduced total oxide charge and SiO2nullSi interface trap density parameters uses precursor densified thin oxide layers, to improve the quality of subsequently formed thicker oxide layers, and multiple anneals to remove implant damage and set geometry parameters. After formation of a first dual oxide layer, and a post-oxidation anneal, the oxide is patterned and JTE regions are implanted. Implant-based near surface crystalline damage is annealed out in a non-oxidizing ambient, and JTE dopants are partially driven into adjoining material of the substrate. A thin dense bulk precursor oxide layer is grown on the exposed JTE dopant-implanted surface portions of the substrate, followed by forming the bulk of the JTE oxide in a steam or wet oxygen atmosphere. The substrate is then annealed in a non-oxidizing ambient, to cause a further drive-in of the JTE dopants. The associated reduction in Qox and Dit improves high voltage edge stability.
摘要翻译：用于形成具有降低的总氧化物电荷和SiO 2 -Si界面陷阱密度参数的连接终止延伸（JTE）氧化物的方法使用前体致密的薄氧化物层，以改善随后形成的较厚氧化物层的质量，以及多次退火以去除植入物损伤并设置几何参数。在形成第一双氧化物层和后氧化退火之后，对氧化物进行图案化并注入JTE区域。基于种植体的近表面结晶损伤在非氧化环境中退火，并且JTE掺杂剂被部分驱动到基底的相邻材料中。在衬底的暴露的JTE掺杂剂注入的表面部分上生长薄的密集体前体氧化物层，然后在蒸汽或湿氧气氛中形成大部分的JTE氧化物。然后将衬底在非氧化环境中退火，以引起JTE掺杂剂的进一步驱入。相关的Qox和Dit降低提高了高电压边缘的稳定性。

65. 发明申请

US20010024866A1 Method of manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20010024866A1
公开(公告)日：2001-09-27
申请号：US09814390
申请日：2001-03-21
申请人： U.S. Philips Corporation
发明人： Darren T. Murley , Michael J. Trainor
IPC分类号： H01L021/20 , H01L021/36 , H01L021/26 , H01L021/324 , H01L021/42 , H01L021/477 , H01L021/84
CPC分类号： H01L29/66757 , H01L29/78603 , H01L29/78675
摘要： A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8null) electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8null). The method comprising the steps of applying a foil (2) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (4) over a supporting substrate (1); and heating the semiconductor layer (4) so as to crystallise the semiconductor layer (4) from regions exposed to the CEM of the foil (2). The method may further comprise the step of providing a patterned barrier layer (3) between the foil (2) and the semiconductor layer (4) wherein the semiconductor layer (4) is crystallised from regions exposed through vias in the barrier layer (3) to the CEM of the foil (2). Also disclosed is a TFT (10) manufactured by the same, and an active matrix device (20) comprising a row and column array of active elements (22) wherein each element (22) is associated with such a TFT (10) connected to corresponding row (24) and column (23) conductors.
摘要翻译：公开了一种制造TFT（10）的方法，其包括由半导体层（4），栅极绝缘层（7）和栅极绝缘层（7）形成的半导体沟道（6）连接的源极（8）和漏极（8“ 栅电极（8'）。该方法包括以下步骤：施加包含结晶增强材料（CEM）的箔（2）并将半导体层（4）沉积在支撑衬底（1）上; 以及加热半导体层（4）以使半导体层（4）从暴露于箔（2）的CEM的区域结晶。该方法还可以包括在箔（2）和半导体层（4）之间提供图案化阻挡层（3）的步骤，其中半导体层（4）从通过阻挡层（3）中的通孔暴露的区域结晶化，到箔（2）的CEM。还公开了由其制造的TFT（10）以及包括有源元件（22）的行和列阵列的有源矩阵器件（20），其中每个元件（22）与这样的TFT（10）相关联，相应的行（24）和列（23）导体。

66. 发明申请

US20010021554A1 Method for fabricating a semiconductor component 有权
标题翻译：半导体部件的制造方法
公开(公告)号：US20010021554A1
公开(公告)日：2001-09-13
申请号：US09793351
申请日：2001-02-26
发明人： Joachim Hopfner
IPC分类号： H01L021/8242 , H01L021/20 , H01L021/26
CPC分类号： H01L27/11502 , H01L21/3105 , H01L27/10855 , H01L27/11507 , H01L28/55
摘要： In a method for fabricating a semiconductor component, a first oxide layer is produced above a substrate. A capacitor is formed above the first oxide layer. The capacitor includes a bottom electrode and a top electrode and a metal-oxide-containing capacitor material layer deposited in between the electrodes. Prior to forming the capacitor, a plasma doping method is used to dope the first oxide layer with a barrier substance which builds up a hydrogen diffusion barrier in the first oxide layer.
摘要翻译：在半导体部件的制造方法中，在基板的上方形成第一氧化物层。在第一氧化物层上形成电容器。电容器包括沉积在电极之间的底部电极和顶部电极以及含金属氧化物的电容器材料层。在形成电容器之前，使用等离子体掺杂方法以在第一氧化物层中形成氢扩散阻挡层的阻挡物质掺杂第一氧化物层。

67. 发明申请

US20040266223A1 Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device 有权
标题翻译：激光照射方法，激光照射装置以及半导体装置的制造方法
公开(公告)号：US20040266223A1
公开(公告)日：2004-12-30
申请号：US10896007
申请日：2004-07-22
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Koichiro Tanaka , Tomoaki Moriwaka
IPC分类号： H01L021/26 , G11B011/00 , G21G005/00 , H01L021/00
CPC分类号： H01L21/2026 , B23K26/066 , H01L21/02683 , H01L21/02686 , H01L21/268 , H01L27/12 , H01L27/1285 , H01S3/005
摘要： Attenuation regions of laser light are removed or reduced in size using a slit located in the immediate vicinity of a surface to be irradiated so that a steep energy distribution is obtained in the end portions of the laser light. The reason why the slit is located in the immediate vicinity of the surface to be irradiated is to suppress the spread of the laser light. In addition, the attenuation regions of the laser light are folded by using a mirror instead of the slit to increase energy densities in the attenuation regions by one another so that a steep energy density distribution is obtained in the end portions of the laser light.
摘要翻译：使用位于要照射的表面附近的狭缝，去除或减小激光的衰减区域，使得在激光的端部获得陡峭的能量分布。狭缝位于待照射表面附近的原因是为了抑制激光的扩散。此外，通过使用反射镜而不是狭缝折射激光的衰减区域，以使衰减区域中的能量密度相互增加，使得在激光的端部获得陡峭的能量密度分布。

68. 发明申请

US20040241968A1 Production method and production device for semiconductor device 审中-公开
标题翻译：半导体器件的生产方法和生产装置
公开(公告)号：US20040241968A1
公开(公告)日：2004-12-02
申请号：US10487987
申请日：2004-02-27
发明人： Shigemi Murakawa , Shinichi Sato , Toshio Nakanishi
IPC分类号： H01L021/26 , H01L021/42 , H01L021/04
CPC分类号： H01J37/32192 , H01L21/26513 , H01L21/268 , H01L21/324 , H01L29/78
摘要： An impurity diffusion layer that structures a source region (15) and a drain electrode (16) of a pMOS 11 is formed extremely shallow, with a depth of approximately 50 nm. The extremely shallow impurity diffusion layer is formed by carrying out annealing process using RLSA plasma, after ion implantation processing at a low energy. In the annealing process, only silicon atoms near the surface of a silicon substrate (12) are selectively excited by the RLSA plasma, and impurity diffusion towards depth direction is suppressed.
摘要翻译：构成pMOS11的源区（15）和漏电极（16）的杂质扩散层形成得非常浅，深度约为50nm。通过在低能量离子注入处理后，通过使用RLSA等离子体进行退火处理来形成极浅的杂质扩散层。在退火过程中，只有硅衬底（12）表面附近的硅原子被RLSA等离子体选择性地激发，并且抑制了向深度方向的杂质扩散。

69. 发明申请

US20040152271A1 Method of forming bottom oxide layer in trench structure 有权
标题翻译：在沟槽结构中形成底部氧化物层的方法
公开(公告)号：US20040152271A1
公开(公告)日：2004-08-05
申请号：US10668454
申请日：2003-09-22
申请人： MOSEL VITELIC, INC.
发明人： Ta-Chung Wu , Yi-Chuan Yang , Shih-Chi Lai , Yew-Jung Chang
IPC分类号： H01L021/42 , H01L021/336 , H01L021/324 , H01L021/26 , H01L021/477
CPC分类号： H01L21/76224 , H01L29/42368 , H01L29/7813
摘要： Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS as a source to deposit an oxide layer on the bottom and sidewall of the trench structure and the semiconductor substrate; and removing the oxide layer on the sidewall of the trench structure substantially completely and the oxide layer on the bottom of the trench structure partially to define the remained oxide layer as the bottom oxide layer.
摘要翻译：本发明的实施例涉及在沟槽结构中形成底部氧化物的方法。在一个实施例中，该方法包括以下步骤：提供半导体衬底并在半导体衬底中形成沟槽结构; 以TEOS作为源进行PECVD处理，以在沟槽结构和半导体衬底的底部和侧壁上沉积氧化物层; 并且基本上完全去除沟槽结构的侧壁上的氧化物层，并且部分地去除沟槽结构的底部上的氧化物层以限定作为底部氧化物层的剩余氧化物层。

70. 发明申请

US20040142581A1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20040142581A1
公开(公告)日：2004-07-22
申请号：US10752993
申请日：2004-01-08
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Setsuo Nakajima
IPC分类号： H01L021/26
CPC分类号： H01L21/02686 , C03C17/22 , C03C2218/32 , H01L21/02672 , H01L21/2026 , H01L27/12 , H01L27/1277 , H01L27/1281 , H01L27/1285 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/66765
摘要： A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the surface of the semiconductor layer and a gate insulating film, in order to achieve a TFT having a good characteristic. In an atmosphere of one kind or a plural kinds of gas selected from hydrogen or inert gas (nitrogen, argon, helium, neon, krypton and xenon), radiation with a laser beam in the first, second and third conditions is carried out in order, wherein the first condition laser beam is radiated for crystallizing a semiconductor film or improving a crystal characteristic; the second condition laser beam is radiated for eliminating an oxide film; and the third condition laser beam is radiated for leveling a surface of the crystallized semiconductor film.
摘要翻译：本发明的目的是提供一种在不增加制造工艺的数量和复杂性以及不劣化晶体特性的情况下调整半导体层的方法，以及用于使半导体层的表面平整以稳定第半导体层的表面和栅极绝缘膜，以实现具有良好特性的TFT。在选自氢或惰性气体（氮气，氩气，氦气，氖气，氪气和氙气）中的一种或多种气体的气氛中，按照第一，第二和第三条件的激光束依次进行其中辐射第一状态激光束以使半导体膜结晶或提高晶体特性; 第二条件激光束被辐射以消除氧化膜; 并且第三条件激光束被照射以使结晶的半导体膜的表面平整。

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