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61. 发明授权

US5677692A High-speed and low-voltage driven analog-to-digital converter 失效
标题翻译：高速和低压驱动的模数转换器
公开(公告)号：US5677692A
公开(公告)日：1997-10-14
申请号：US585761
申请日：1996-01-11
申请人： Hiroshi Hasegawa
发明人： Hiroshi Hasegawa
IPC分类号： H03M1/12 , H03M1/36 , H03M1/44 , H03M1/38
CPC分类号： H03M1/447
摘要： An N-bit A/D converter comprises 2.sup.N cells connected in cascade, wherein the start cell receives an input analog signal and each cell performs a determination operation to produce a determination signal. Each cell comprises a sample and hold circuit, a comparator, and a subtracter. The sample and hold circuit samples an analog value from a first analog signal received from a previous cell and holds the analog value. The comparator compares the analog value with a reference value to produce the determination signal. The subtracter subtracts a subtrahend value from the analog value to produce a second analog signal which is received by a next cell. The next cell receives the output of the cell as the above-mentioned first analog signal and performs the same determination operation as the cell. The cascade-connected cells are controlled with timing clocks so as to perform a pipeline operation such that the cell produces the determination signal when the next cell receives the second analog signal.
摘要翻译： N位A / D转换器包括级联连接的2N个单元，其中起始单元接收输入模拟信号，每个单元执行确定操作以产生确定信号。每个单元包括采样和保持电路，比较器和减法器。采样和保持电路从前一个单元接收的第一个模拟信号中采样一个模拟值，并保存模拟值。比较器将模拟值与参考值进行比较，以产生确定信号。减法器从模拟值中减去减数值以产生由下一个单元接收的第二模拟信号。下一个单元接收作为上述第一模拟信号的单元的输出，并执行与单元相同的确定操作。用定时时钟控制级联连接的小区，以便执行流水线操作，使得当下一个小区接收到第二模拟信号时，小区产生确定信号。

62. 发明授权

US4725813A MOS type circuit device 失效
标题翻译： MOS型电路装置
公开(公告)号：US4725813A
公开(公告)日：1988-02-16
申请号：US853293
申请日：1986-04-17
申请人： Yoshinori Miyada
发明人： Yoshinori Miyada
IPC分类号： H03K19/0944 , G05F1/46 , H03K17/687 , H03K19/003 , H03K19/094 , H03M1/00 , H03M1/66
CPC分类号： G05F1/462 , H03K19/00384 , H03M1/72 , H03K2217/0018 , H03M1/447
摘要： A MOS type circuit which has a high switching speed and which is free from the substrate bias effect includes a MOS transistor having a source electrode, a back gate region, a drain electrode and a gate electrode, and an amplifier having a gain of about "1", with the input and output of the amplifier being respectively coupled to the source electrode and the back gate electrode of the MOS transistor.
摘要翻译：具有高开关速度且不具有衬底偏置效应的MOS型电路包括具有源电极，背栅区，漏电极和栅电极的MOS晶体管，以及具有约“ 1“，放大器的输入和输出分别耦合到MOS晶体管的源电极和背栅电极。

63. 发明授权

US4689607A Bidirectional transconductance amplifier 失效
标题翻译：双向跨导放大器
公开(公告)号：US4689607A
公开(公告)日：1987-08-25
申请号：US7717
申请日：1987-01-28
申请人： Jeffrey I. Robinson
发明人： Jeffrey I. Robinson
IPC分类号： H03M1/44
CPC分类号： H03M1/447 , H03F3/62
摘要： An apparatus for converting an input voltage into a related output current, is disclosed and generally comprises: a resistance means in series with the voltage input; first and second double output current mirrors, wherein each output of the first double output mirror is connected to a corresponding output of the second double output mirror, and the inputs of the double output current mirrors are connected; and an operational amplifier with the inverting input connected to ground, the noninverting input connected to the resistance means, and the op amp output connected to the inputs of the first and second double output mirrors, wherein first outputs of the first and second double output mirrors are connected to the noninverting input of the operational amplifier, and the second outputs of the first and second double output mirrors are connected to the output current. The disclosed transconductance amplifier is advantageously used to transform an input voltage into an input current for a continuous time analog to digital converter which uses current steering techniques.
摘要翻译：公开了一种用于将输入电压转换为相关输出电流的装置，其通常包括：与电压输入串联的电阻装置; 第一和第二双输出电流镜，其中第一双输出反射镜的每个输出连接到第二双输出反射镜的对应输出，并且双输出电流镜的输入被连接; 以及运算放大器，其反相输入端连接到地，连接到电阻装置的同相输入端和连接到第一和第二双输出反射镜的输入的运算放大器输出，其中第一和第二双输出反射镜的第一输出连接到运算放大器的同相输入，第一和第二双输出反射镜的第二输出端连接到输出电流。所公开的跨导放大器有利地用于将输入电压变换为使用当前转向技术的连续时间模数转换器的输入电流。

64. 发明申请

US20190131996A1 DIGITAL-TO-ANALOG CONVERTERS HAVING A RESISTIVE LADDER NETWORK 审中-公开
公开(公告)号：US20190131996A1
公开(公告)日：2019-05-02
申请号：US15996082
申请日：2018-06-01
申请人： SK hynix Inc.
发明人： Keunjin Chang
IPC分类号： H03M1/18 , H03M1/44
CPC分类号： H03M1/183 , H03M1/00 , H03M1/0612 , H03M1/0646 , H03M1/1057 , H03M1/447 , H03M1/66 , H03M1/785 , H03M1/80
摘要： According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a plurality of paths corresponding to bit currents, respectively. The digital-to-analog converter may include a switching circuit configured to include a plurality of weighted elements respectively coupled to the paths. The digital-to-analog converter may include a reference voltage setting circuit coupled to the weighted elements and the paths, and configured to minimize a variation of threshold voltages of the weighted elements.

65. 发明申请

US20180183458A1 HYBRID FLASH ARCHITECTURE OF SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER 审中-公开
公开(公告)号：US20180183458A1
公开(公告)日：2018-06-28
申请号：US15853779
申请日：2017-12-23
申请人： Avnera Corporation
发明人： Wai Lee , Jianping Wen , Garry N. Link
IPC分类号： H03M1/46 , H03M1/10 , H03M1/44
CPC分类号： H03M1/462 , H03M1/1033 , H03M1/188 , H03M1/447 , H03M1/468
摘要： The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

66. 发明申请

US20050242982A1 Switched-current analogue-to-digital converter 有权
标题翻译：开关电流模数转换器
公开(公告)号：US20050242982A1
公开(公告)日：2005-11-03
申请号：US10521670
申请日：2003-07-08
申请人： John Hughes
发明人： John Hughes
IPC分类号： H03M1/44 , H03M1/06 , H03M1/38
CPC分类号： H03M1/0695 , H03M1/447
摘要： An current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit (120, 130, 135) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (140). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits (140, 140″) may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (Si′ Si″ can be multiplexed to double the conversion rate.
摘要翻译：电流模式模拟 - 数字转换器使用转换级，其使用两相时钟进行操作，并且需要在仅一个相位期间存在输入信号。采样和保持电路（120,130,135）在第一时钟相位期间对输入信号进行采样，并且在第二时钟相位期间，通过无反冲比较器电路从保持的输入电流的反射镜产生量化位值（140）。同样在第二时钟阶段期间，使用量化值和保持的输入电流的非镜像版本来生成残差。可选地，可以使用两个比较器电路（140,140“）来提供两级量化，使由电流镜引入的误差能够被冗余有符号数字算法校正。转换级的两条流水线可以被多路复用成两倍的转换速率。

67. 发明授权

US06958723B1 Method and apparatus for reducing noise in analog-to-digital converter devices 有权
标题翻译：降低模数转换器装置噪声的方法和装置
公开(公告)号：US06958723B1
公开(公告)日：2005-10-25
申请号：US10803128
申请日：2004-03-17
申请人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua , William David Smith
发明人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua , William David Smith
IPC分类号： H03M1/08 , H03M1/38 , H03M1/44
CPC分类号： H03M1/08 , H03M1/447
摘要： An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.
摘要翻译：模数转换器装置具有多个级。每个级包括具有第一和第二放大器单元的残余放大器。每个放大器单元具有第一输入轨迹，第二输入轨迹和输出轨迹。放大器单元合作在第一输入轨迹处接收差分输入数据信号。 DC电平设定信号单元与第二输入轨迹耦合，并且在第一电流方向上提供直流电平设定电流。逆流信号产生单元经由与第二输入轨迹共同的单个耦合轨迹与第二输入轨迹耦合，并且在与第一电流方向相反的第二电流方向上向第二输入轨迹提供控制电流信号。控制电流信号为每个放大器单元提供直流电平控制。

68. 发明授权

US06891495B2 Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US06891495B2
公开(公告)日：2005-05-10
申请号：US10453378
申请日：2003-06-02
申请人： Jiann-Jong Chen , Po-Jen Huang , Hung-Yih Lin , Cheng-Tung Wang
发明人： Jiann-Jong Chen , Po-Jen Huang , Hung-Yih Lin , Cheng-Tung Wang
IPC分类号： H03M1/44 , H03M1/38
CPC分类号： H03M1/447
摘要： An analog-to-digital converter including analog-to-digital converting units connected in serial. The current comparator includes a current input terminal to receive a sampling current, a reference current input terminal to receive a reference current and a bit output terminal for outputting a bit signal. The current operation circuit includes a current output terminal for outputting a compared current according to the sampling current and the reference current. The operation controlling terminal selects the compared current according to the bit signal. The controlling terminal receives a clock signal to latch the bit signal. The analog-to-digital converting units output the bit signals in sequence in a period of the clock signal.
摘要翻译：包括串行连接的模数转换单元的模数转换器。电流比较器包括用于接收采样电流的电流输入端子，用于接收参考电流的参考电流输入端子和用于输出位信号的位输出端子。电流运算电路包括用于根据采样电流和参考电流输出比较电流的电流输出端子。操作控制终端根据位信号选择被比较的电流。控制终端接收时钟信号以锁存比特信号。模数转换单元在时钟信号的周期内依次输出位信号。

69. 发明授权

US06392582B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06392582B1
公开(公告)日：2002-05-21
申请号：US09662605
申请日：2000-09-14
申请人： Hiroyuki Nakamura
发明人： Hiroyuki Nakamura
IPC分类号： H03M112
CPC分类号： H03M1/125 , G01R19/2509 , H03M1/44 , H03M1/447
摘要： This invention includes a current output sensor, and a current AD conversion means which is connected to the output side of the current output sensor and has a current mirror circuit arranged on the input side of a comparator in order to directly A/D-convert an output from the current output sensor. A signal can be stably processed with a small circuit scale and low current consumption.
摘要翻译：本发明包括电流输出传感器和电流AD转换装置，其连接到电流输出传感器的输出侧，并且具有布置在比较器的输入侧的电流镜电路，以便直接A / D转换从当前输出传感器输出。可以以小的电路规模和低电流消耗稳定地处理信号。

70. 发明授权

US4745395A Precision current rectifier for rectifying input current 失效
标题翻译：精密电流整流器整流输入电流
公开(公告)号：US4745395A
公开(公告)日：1988-05-17
申请号：US7714
申请日：1987-01-28
申请人： Jeffrey I. Robinson
发明人： Jeffrey I. Robinson
IPC分类号： H03M1/44
CPC分类号： H03M1/447 , H02M7/217
摘要： A current rectifier is provided and generally comprises: a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I.sub.in ; and a first current mirror with its input connected to the drain of the n-channel transistor, and its output connected to the drain of the p-channel transistor. The current rectifier preferably also includes a second current mirror with the drain of the p-channel transistor as an input to the second current mirror and the rectified output current I.sub.out as an output of the second current mirror. If an offset to the rectified current is desired, a third current mirror having a bias or offset current as an input and the output of the second current mirror as an output may be included.
摘要翻译：提供电流整流器，并且通常包括：p沟道晶体管和n沟道晶体管，其具有连接到地的公共栅极和连接到输入电流Iin的公共源; 以及第一电流镜，其输入端连接到n沟道晶体管的漏极，其输出端连接到p沟道晶体管的漏极。电流整流器优选地还包括第二电流镜，其中p沟道晶体管的漏极作为第二电流镜的输入端和被整流的输出电流Iout作为第二电流镜的输出。如果需要对整流电流的偏移，则可以包括具有偏置电流或偏移电流作为输入的第三电流镜和作为输出的第二电流镜的输出。

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