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61. 发明公开

EP0055570A3 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：EP0055570A3
公开(公告)日：1983-01-26
申请号：EP81305982
申请日：1981-12-21
申请人： FUJITSU LIMITED
发明人： Nishiuchi, Koichi
IPC分类号： H03K19/017 , H03K19/003 , H03K19/094 , H03K19/20
CPC分类号： H03K19/09445 , H03K19/01721 , H03K19/09441
摘要： A logic circuit has a first logic gate (G 6 ), having a plurality of inputs (a and b) and an output (m), and a second logic gate comprising a driving FET (Q 6 ) and a plurality of load FET's (T 6 ' and T 6 ). The gate of the driving FET (Q 6 ) is connected to the output (m) of the first logic gate and the gates of the load FET's (T 6 ' and T s ) are connected to respective inputs (a, b) of the first logic gate. The driving FET and the load FET's are connected in series. A pair of FET's (T', T), one depletion-mode and one enhancement-mode, with their drains, sources and gates respectively connected in common may be used in place of a single load FET.
摘要翻译：包括多输入NOR门，多个负载场效应晶体管（FET）和驱动FET的逻辑电路，负载FET和驱动FET在电源之间彼此串联连接，逻辑输出源自负载FET和驱动FET的连接点。 NOR门的输入与负载FET的输入相同。 NOR门的输入端连接到负载FET的相应栅极，NOR门的输出端连接到驱动FET的栅极。

62. 发明公开

EP0053798A3 Monolithic integrated buffer inverter 失效
标题翻译：单片集成缓冲器逆变器
公开(公告)号：EP0053798A3
公开(公告)日：1983-01-05
申请号：EP81110096
申请日：1981-12-03
申请人： Deutsche ITT Industries GmbH , ITT INDUSTRIES INC.
发明人： Pernyeszi, Joseph , Gollinger, Wolfgang, Dipl.Ing
IPC分类号： H03K19/094 , H02K05/02 , H03F03/30
CPC分类号： H03K19/09445 , H03K19/018507 , H03K19/09446

63. 发明公开

EP0047366A1 Transistor driver circuit 失效
标题翻译：晶体管驱动电路。
公开(公告)号：EP0047366A1
公开(公告)日：1982-03-17
申请号：EP81105227.3
申请日：1981-07-06
申请人： International Business Machines Corporation
发明人： Pricer, Wilbur David
IPC分类号： H03K5/02
CPC分类号： H03K5/023 , H03K19/09445
摘要： The circuit (Fig. 1) rapidly charges and discharges a load capacitor by sensing the direction of transients at an internal node (12) of the circuit which is selectively isolated from a capacitive output node (26) to produce significant load current during upward transients. In an embodiment of the invention, the circuit includes a driver device (10) and first (18), second (24) and third (30) field effect transistors. The first transistor (18) is connected between a voltage supply terminal (20) and the driver device (10) forming an internal node (12) and acts as a current source pulling up the internal node. The second transistor (18) is connected between the internal node (12) and an output node (26) and is arranged to selectively isolate the internal node from the output node, with isolation increasing during a positive transient to allow maximum drive to the third transistor connected between the voltage supply terminal and the output node to produce increased output current. The second transistor (26) is also arranged to minimize the isolation between the internal and output nodes (12, 26) during negative transients to rapidly discharge the output node.

64. 发明公开

EP2264900A1 Low-current inverter circuit 有权
标题翻译：逆变器Stromstärke
公开(公告)号：EP2264900A1
公开(公告)日：2010-12-22
申请号：EP09162993.1
申请日：2009-06-17
申请人： Epcos AG
发明人： Spits, Erwin
IPC分类号： H03K19/094 , H03K19/0944
CPC分类号： H03K19/09418 , H03K19/09407 , H03K19/09445
摘要： The circuit comprises an E-mode transistor (E3) with gate-source junction, a D-mode transistor (D) with gate-source junction, a component generating a voltage drop (E1, E2) between the source (4) of the D-mode transistor and the drain (2) of the E-mode transistor, and a connection (7) between the drain (2) of the E-mode transistor and the gate (6) of the D-mode transistor. The gate (3) of the E-mode transistor is provided for an input signal (IN), and the drain (2) of the E-mode transistor is provided for an output signal (OUT). The circuit enables the operation of logic circuitry in GaAs technology with only low currents flowing.
摘要翻译：该电路包括具有栅极 - 源极结的E型晶体管（E3），具有栅极 - 源极结的D型晶体管（D），在源极（4）的源极（4）之间产生电压降（E1，E2） D型晶体管和E型晶体管的漏极（2）以及E型晶体管的漏极（2）与D型晶体管的栅极（6）之间的连接（7）。 E模式晶体管的栅极（3）用于输入信号（IN），并且为输出信号（OUT）提供E模式晶体管的漏极（2）。该电路使得GaAs技术中逻辑电路的运行只有低电流流动。

65. 发明公开

EP2264899A1 Low-current logic-gate circuit 有权
标题翻译： Stromstärke的Logikgatterschaltung
公开(公告)号：EP2264899A1
公开(公告)日：2010-12-22
申请号：EP09162990.7
申请日：2009-06-17
申请人： Epcos AG
发明人： Spits, Erwin , van den Oever, Léon C. M.
IPC分类号： H03K19/094 , H03K19/0944
CPC分类号： H03K19/09418 , H03K19/09407 , H03K19/09445
摘要： The circuit comprises E-mode transistors (E3, E4, E5) with gate-source junction, a D-mode transistor (D) with gate-source junction, a component generating a voltage drop (E1, E2) between the source (4) of the D-mode transistor and the drain (2) of an E-mode transistor provided as a signal output (OUT), a connection (7) between this drain (2) of the E-mode transistor and the gate (6) of the D-mode transistor, and a signal input (IN) at the gates (3, 24, 27) of the E-mode transistors. The E-mode transistors are arranged to operate as NAND and/or NOR logics. The circuit enables the operation of logic circuitry in GaAs technology with only low currents flowing.
摘要翻译：该电路包括具有栅极 - 源极结的E型晶体管（E3，E4，E5），具有栅极 - 源极结的D型晶体管（D），在源极（4）之间产生电压降（E1，E2））和作为信号输出（OUT）提供的E型晶体管的漏极（2），E型晶体管的漏极（2）和栅极（6）之间的连接（7））和在E模式晶体管的栅极（3,24,27）处的信号输入（IN）。 E模式晶体管被布置为以NAND和/或NOR逻辑运行。该电路使得GaAs技术中逻辑电路的运行只有低电流流动。

66. 发明授权

EP0048922B1 Dynamic signal generation circuit 失效
标题翻译：动态信号发生电路
公开(公告)号：EP0048922B1
公开(公告)日：1986-04-23
申请号：EP81107500.1
申请日：1981-09-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Furuyama, Toru
IPC分类号： H03K19/096 , H03K5/02
CPC分类号： H03K19/0013 , H03K5/023 , H03K19/01714 , H03K19/09445

67. 发明授权

EP0053798B1 Monolithisch integrierter Puffer-Inverter 失效
标题翻译：单片集成缓冲器逆变器
公开(公告)号：EP0053798B1
公开(公告)日：1985-08-28
申请号：EP81110096.5
申请日：1981-12-03
申请人： Deutsche ITT Industries GmbH , ITT INDUSTRIES, INC.
发明人： Pernyeszi, Joseph , Gollinger, Wolfgang, Dipl.Ing
IPC分类号： H03K19/094 , H02K5/02 , H03F3/30
CPC分类号： H03K19/09445 , H03K19/018507 , H03K19/09446

68. 发明公开

EP0120992A2 AND-gate driver circuit 失效
标题翻译： AND门控制电路。
公开(公告)号：EP0120992A2
公开(公告)日：1984-10-10
申请号：EP83111939.1
申请日：1983-11-29
申请人： International Business Machines Corporation
发明人： Boyle, David Henry , Kouba, Daniel John
IPC分类号： H03K19/094 , H03K19/017
CPC分类号： H03K19/09445 , H03K19/01714
摘要： A "natural" threshold device (4) is serially connected between the gate of an output low threshold FET device (6) and the input node to the circuit so as to provide current flow from the input node to the gate of the FET device (6) as the input waveform begins to rise, and yet to provide sufficient resistance in the gate circuit of the low threshold device so as to prevent backward flow of current from the gate as the potential of the output node rises. This increases the conductivity of the output device (6), thereby providing a faster rise time for the output waveform.

69. 发明授权

EP0051157B1 A logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：EP0051157B1
公开(公告)日：1984-09-26
申请号：EP81107922.7
申请日：1981-10-05
申请人： International Business Machines Corporation
发明人： Cases, Moises , Kraft, Wayne Richard , Moore, Victor Stewart , Stahl, William Leonard Jr. , Thoma, Nandor Gyorgy
IPC分类号： H03K19/177
CPC分类号： H03K19/1778 , H01L27/0883 , H01L27/112 , H03K19/09445 , H03K19/1772 , H03K19/17728

70. 发明公开

EP0051157A1 A logic performing cell for use in array structures 失效
标题翻译：在解放军的结构使用逻辑链路执行单元。
公开(公告)号：EP0051157A1
公开(公告)日：1982-05-12
申请号：EP81107922.7
申请日：1981-10-05
申请人： International Business Machines Corporation
发明人： Cases, Moises , Kraft, Wayne Richard , Moore, Victor Stewart , Stahl, William Leonard Jr. , Thoma, Nandor Gyorgy
IPC分类号： H03K19/177
CPC分类号： H03K19/1778 , H01L27/0883 , H01L27/112 , H03K19/09445 , H03K19/1772 , H03K19/17728
摘要： A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines (I1, I2, ..., IN). Elements (T1, T2, ..., TN) in the form of a three terminal device are located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates (T1, T2, ..., TN) are connected in groups of series strings (50, 51) which are connected in parallel to a recombination line. These groups of series connected transfer gates (T1, ...; T (N/2 + 1), ...) comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates (T1, ...; T(N/2 + 1) ...) establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.

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