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61. 发明申请

US20040061148A1 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
标题翻译：具有电隔离电荷存储区域的大容量CMOS工艺中的单晶体管浮体DRAM单元
公开(公告)号：US20040061148A1
公开(公告)日：2004-04-01
申请号：US10676695
申请日：2003-09-30
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu
IPC分类号： H01L027/148 , H01L029/768
CPC分类号： H01L27/108 , H01L27/0214 , H01L27/10802 , H01L27/10873 , H01L29/7841
摘要： A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.
摘要翻译：提供了一个单晶体管浮体（1T / FB）动态随机存取存储器（DRAM）单元，其包括使用与标准CMOS工艺兼容的工艺制造的场效应晶体管。场效应晶体管包括位于源极区域和漏极区域之间的第一导电类型的源极区域和漏极区域以及与第一导电类型相反的第二导电类型的浮动体区域。第一导电类型的掩埋区域位于源极区域，漏极区域和浮体区域的下方。掩埋区域有助于形成耗尽区，其位于掩埋区域与源极区域，漏极区域和浮体区域之间。浮体区由此被耗尽区隔离。可以将偏置电压施加到掩埋区域，从而控制1T / FB DRAM单元中的漏电流。

62. 发明申请

US20030151072A1 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US20030151072A1
公开(公告)日：2003-08-14
申请号：US10374956
申请日：2003-02-25
申请人： Monolithic System Technology, Inc.
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L031/0328
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

63. 发明申请

US20030151071A1 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US20030151071A1
公开(公告)日：2003-08-14
申请号：US10374917
申请日：2003-02-25
申请人： Monolithic System Technology, Inc.
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L031/0328
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

64. 发明申请

US20020008271A1 Non-volatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US20020008271A1
公开(公告)日：2002-01-24
申请号：US09948163
申请日：2001-09-06
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： H01L029/76 , H01L027/108
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory (NVM) system includes a NVM cell having: a semiconductor region having a first conductivity type; a gate dielectric layer located over the semiconductor region; a gate electrode located over the gate dielectric layer; a source region and a drain region of a second conductivity type, opposite the first conductivity type, located in the semiconductor region and aligned with the gate electrode; a crown electrode having a base that contacts the gate electrode and walls that extend vertically from the base region, away from the gate electrode; a dielectric layer located over the crown electrode, wherein the dielectric layer extends over at least interior surfaces of the walls; and a plate electrode located over the dielectric layer, wherein the plate electrode extends over at least interior surfaces of the walls.
摘要翻译：非易失性存储器（NVM）系统包括具有：具有第一导电类型的半导体区域的NVM单元; 位于所述半导体区域上方的栅介质层; 位于所述栅极电介质层上方的栅电极; 与第一导电类型相反的第二导电类型的源极区域和漏极区域，位于半导体区域中并与栅电极对准; 冠电极，其具有与栅电极接触的基极和从基极区域垂直延伸的壁，远离栅电极; 位于所述冠状电极之上的电介质层，其中所述电介质层至少在所述壁的内表面上延伸; 以及位于所述电介质层上方的平板电极，其中所述平板电极至少在所述壁的内表面上延伸。

65. 发明授权

US6128700A System utilizing a DRAM array as a next level cache memory and method for operating same 失效
标题翻译：利用DRAM阵列作为下一级高速缓冲存储器的系统及其操作方法
公开(公告)号：US6128700A
公开(公告)日：2000-10-03
申请号：US942254
申请日：1997-10-01
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C11/406 , G11C11/4076 , G11C11/4096 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus. A structure and method control the refresh and internal operations of the DRAM array.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线，以及包括连接到CPU总线的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。结果，DRAM阵列的预充电对CPU总线是透明的。一种结构和方法来控制DRAM阵列的刷新和内部操作。

66. 发明授权

US5940088A Method and structure for data traffic reduction for display refresh 失效
标题翻译：用于显示刷新的数据流量降低的方法和结构
公开(公告)号：US5940088A
公开(公告)日：1999-08-17
申请号：US501332
申请日：1995-07-12
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： G09G5/395 , G09G5/00
CPC分类号： G09G5/395 , G09G2360/12 , G09G2360/121
摘要： A method and structure for performing a screen refresh operation in a video processing system which includes a frame buffer memory and a display controller coupled to a system bus. A status bit memory is used to store status bits which represent the repetitive characteristics of pixel data stored in the frame buffer memory. The status bits are provided to the display controller. In response, the display controller determines whether to provide pixel data by regenerating pixel data previously retrieved from the frame buffer memory or by accessing the frame buffer memory.
摘要翻译：一种用于在包括帧缓冲存储器和耦合到系统总线的显示控制器的视频处理系统中执行画面刷新操作的方法和结构。状态位存储器用于存储表示存储在帧缓冲存储器中的像素数据的重复特性的状态位。状态位提供给显示控制器。作为响应，显示控制器通过再生先前从帧缓冲存储器检索的像素数据或通过访问帧缓冲存储器来确定是否提供像素数据。

67. 发明授权

US5829026A Method and structure for implementing a cache memory using a DRAM array 失效
标题翻译：使用DRAM阵列实现高速缓冲存储器的方法和结构
公开(公告)号：US5829026A
公开(公告)日：1998-10-27
申请号：US812000
申请日：1997-03-05
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0893
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. The DRAM array is operated at a higher frequency than the frequency of the CPU bus clock signal, thereby reducing the access latency of the DRAM array. By operating the DRAM array at a higher frequency than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线，以及包括连接到CPU总线的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。 DRAM阵列的操作频率高于CPU总线时钟信号的频率，从而降低了DRAM阵列的访问延迟。通过以比CPU总线更高的频率操作DRAM阵列，为DRAM阵列的预充电提供了额外的时间。结果，DRAM阵列的预充电对CPU总线是透明的。

68. 发明授权

US5737587A Resynchronization circuit for circuit module architecture 失效
标题翻译：电路模块架构的再同步电路
公开(公告)号：US5737587A
公开(公告)日：1998-04-07
申请号：US473633
申请日：1995-06-06
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F5/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/40 , G11C29/00 , G11C29/48 , H01L21/66 , H01L27/02 , H04L25/02 , G06F1/04
CPC分类号： H04L25/026 , G06F12/0661 , G06F13/4077 , G06F5/16 , G11C29/006 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/832 , G11C29/88 , H01L22/22 , G06F11/006 , G06F11/10 , G06F11/1666 , H01L27/0203 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.
摘要翻译：具有通过I / O总线耦合到存储器控制器的几个存储器件的存储器系统，每个存储器件包括通过内部总线耦合到芯片I / O接口的多个存储器模块。该系统包括用于以减小的CMOS摆动驱动I / O总线的电路，用于在一个总线方向上以完全CMOS摆动驱动内部总线并且在另一个总线方向上以减小的CMOS摆幅驱动内部总线的电路列地址产生电路，用于允许在解码器延迟被消除的情况下访问顺序寻址的数据;以及电路，用于将来自源时钟的数据重新同步到具有降低的访问延迟代价的目的地时钟。同时将数据写入多个电路模块会显着增加存储器的写入带宽。还包括动态基地址映射到地址空间，跨多个存储器模块的读或写操作，新颖的I / O总线格式以及用于测试冗余存储器子阵列的协议和测试模式。

69. 发明授权

US5708624A Method and structure for controlling internal operations of a DRAM array 失效
标题翻译：用于控制DRAM阵列的内部操作的方法和结构
公开(公告)号：US5708624A
公开(公告)日：1998-01-13
申请号：US757866
申请日：1996-11-27
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C7/10 , G11C8/18 , G11C11/4076 , G11C11/4091 , G11C7/00
CPC分类号： G11C8/18 , G11C11/4076 , G11C11/4091 , G11C7/1072
摘要： A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and/or falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a first transition of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before a second transition of the clock signal occurs. The second transition is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before a third transition of the clock signal. The third transition of the clock signal is then used to initiate the column address decoding operation of the DRAM array. In an alternative embodiment, the column address decoding is initiated when a column access (CAS#) signal is asserted and the clock signal undergoes the third transition. The first, second and third transitions can be consecutive or non-consecutive edges of the clock signal. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes.
摘要翻译：响应于行访问（RAS＃）信号和时钟信号的上升沿和/或下降沿来控制对DRAM阵列的访问的定时的方法和结构。当接收到行访问信号并且检测到时钟信号的第一次转换时，行地址解码和均衡电路的去激活。在时钟信号的第二次转换发生之前，行地址解码和均衡电路的去激活完成。然后第二个转变用于启动DRAM阵列的读出放大器的导通。读出放大器在时钟信号的第三次转换之前导通。时钟信号的第三次转换然后用于启动DRAM阵列的列地址解码操作。在替代实施例中，当列访问（CAS＃）信号被断言并且时钟信号经历第三转换时，启动列地址解码。第一，第二和第三转换可以是时钟信号的连续或不连续的边缘。包括测试模式，允许DRAM阵列异步运行以进行测试。

70. 发明授权

US5666480A Fault-tolerant hierarchical bus system and method of operating same 失效
标题翻译：容错分层总线系统及其操作方法
公开(公告)号：US5666480A
公开(公告)日：1997-09-09
申请号：US484063
申请日：1995-06-06
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： G06F12/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/00 , G06F13/40 , G11C29/00 , G11C29/04 , G11C29/48 , H01L21/66 , H01L27/02 , H04L5/14 , H04L25/02 , G06F11/34
CPC分类号： H04L25/0272 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/832 , G11C29/88 , H01L22/22 , H04L25/026 , H04L5/1461 , G06F11/006 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , G11C29/81 , G11C5/04 , H01L27/0203 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.
摘要翻译：容错的高速晶片秤系统包括多个功能模块，对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。该总线包括分段成多个总线线路，并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。通过：1）使用小块大小（512K位）作为内存模块; 2）使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3）使用网格结构为总线提供互联网络的全局冗余; 4）使用由13条信号线组成的较窄的总线，使总线占用的总面积较小; 5）使用由可编程开关和可编程总线收发器连接的分段总线，以便于轻松隔离总线缺陷; 6）使用专用电路进行总线收发器和异步握手，方便动态总线配置; 7）使用可编程控制寄存器，方便运行时总线重新配置; 8）使用备用总线为总线提供局部冗余; 和9）在内存模块中使用备用行和列提供局部冗余，获得分层总线中的高缺陷容限。

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