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61. 发明申请

US20150093878A1 FINFET FABRICATION METHOD 有权
公开(公告)号：US20150093878A1
公开(公告)日：2015-04-02
申请号：US14044533
申请日：2013-10-02
申请人： GLOBAL FOUNDRIES Inc.
发明人： Xusheng Wu , Wanxun He , Hongliang Shen
IPC分类号： H01L21/762 , H01L29/78 , H01L27/088 , H01L29/66
CPC分类号： H01L27/0886 , H01L21/0217 , H01L21/3086 , H01L21/31111 , H01L21/76224 , H01L21/823431 , H01L29/0653 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

62. 发明申请

US20150091093A1 INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有双重硅胶接触的集成电路及其制造方法
公开(公告)号：US20150091093A1
公开(公告)日：2015-04-02
申请号：US14043017
申请日：2013-10-01
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Guillaume Bouche , Shao Ming Koh , Jeremy A. Wahl , Andy Wei
IPC分类号： H01L29/417 , H01L27/092
CPC分类号： H01L29/45 , H01L21/823814 , H01L27/092 , H01L29/41725
摘要： Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.
摘要翻译：提供了具有双硅化物触点的集成电路和用于制造具有双硅化物触点的集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括提供具有PFET区域和NFET区域的半导体衬底。该方法选择性地从PFET区域中的第一金属形成第一硅化物接触。此外，该方法从NFET区域中的第二金属选择性地形成第二硅化物接触。第二种金属与第一种金属不同。

63. 发明申请

US20140339645A1 METHODS OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENT INSULATION THICKNESSES ON THE SAME SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICES 有权
标题翻译：在相同的半导体衬底和结构器件上形成具有不同绝缘厚度的半导体器件的方法
公开(公告)号：US20140339645A1
公开(公告)日：2014-11-20
申请号：US13893955
申请日：2013-05-14
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Jun Lian
IPC分类号： H01L21/8234 , H01L29/423 , H01L27/088
CPC分类号： H01L21/823462 , H01L27/088 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material.
摘要翻译：一种方法包括通过形成具有第一厚度的第一厚度的第一层栅极绝缘材料来形成第一和第二器件，形成第二厚度小于第二器件的第二厚度的高k绝缘材料层以及形成接触所述第一层栅极绝缘材料层和所述高k绝缘材料的第一和第二含金属栅电极结构。本文公开的装置包括第一和第二半导体器件，其中第一栅极结构包括绝缘材料层，其具有位于绝缘材料层上并与绝缘材料层接触的第一金属层的第一部分和由层的高k绝缘材料和第一金属层的第二部分位于高k绝缘材料层上并与其接触。

64. 发明申请

US20140315385A1 METHOD OF FORMING A DIELECTRIC FILM 有权
标题翻译：形成电介质膜的方法
公开(公告)号：US20140315385A1
公开(公告)日：2014-10-23
申请号：US13868412
申请日：2013-04-23
申请人： GLOBALFOUNDRIES Inc.
发明人： Hung-Wei Liu , Tsung-Liang Chen , Huang Liu , Zhiguo Sun
IPC分类号： H01L21/02
CPC分类号： H01L21/02112 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/02271 , H01L21/0228 , H01L21/02337 , H01L21/76837
摘要： A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.
摘要翻译：提供了一种可流动氧化物沉积的方法。作为时间或膜深度的函数，氧源气体增加以改变可流动的氧化物性质，使得沉积膜针对存在高纵横比形状的衬底表面附近的间隙填充进行了优化。氧气流速随着膜深度的增加而增加，使得沉积膜对沉积膜的上部区域的平坦化质量进行了优化。

65. 发明申请

US20140291735A1 DOUBLE PATTERNING VIA TRIANGULAR SHAPED SIDEWALL SPACERS 有权
标题翻译：双面图案通过三角形形状的平面空间
公开(公告)号：US20140291735A1
公开(公告)日：2014-10-02
申请号：US13852496
申请日：2013-03-28
申请人： GLOBAL FOUNDRIES, INC.
发明人： HongLiang Shen , Dae-Han Choi , Dae Geun Yang , Jung Yu Hsieh
IPC分类号： H01L21/02 , H01L29/78 , H01L29/423
CPC分类号： H01L21/3086 , H01L21/28114 , H01L21/32135 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.
摘要翻译：制造中的中间半导体结构包括硅半导体衬底，在衬底上的氮化硅（SiN）的硬掩模和在硬掩模上的多晶硅或非晶硅的牺牲层。牺牲层被图案化成侧壁间隔物，用于与侧壁间隔物例如可流动氧化物的组成基本上不同的填充材料的心轴。去除心轴使得侧壁间隔件具有提供粗糙三角形形状的垂直锥形内侧壁和外侧壁。粗糙的三角形侧壁间隔物用作硬掩模以在下面对SiN硬掩模进行图案化。

66. 发明申请

US20140273370A1 TECHNIQUE FOR MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES 有权
标题翻译：制造包含不同阈值电压的晶体管的半导体器件的技术
公开(公告)号：US20140273370A1
公开(公告)日：2014-09-18
申请号：US13799239
申请日：2013-03-13
申请人： GLOBAL FOUNDERIES INC.
发明人： Martin Gerhardt , Stefan Flachowsky , Matthias Kessler
IPC分类号： H01L29/66 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6659
摘要： When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated. Furthermore, the number of implantation steps is decreased compared to conventional manufacturing processes.
摘要翻译：当形成包括具有不同阈值电压的晶体管的半导体器件时，相同导电类型的晶体管的不同阈值电压基本上通过执行不同的光晕注入来定义。由于通常在同一制造步骤中执行的其它植入，例如预非晶化，源极和漏极延伸注入以及额外的扩散工程注入，对于不同的阈值电压可以是相同的，除了常见的晕基植入之外，这些植入可以在同一种植入序列中对相同导电类型的所有晶体管执行。随后可以通过额外的低剂量晕圈注入实现特定晶体管的较高阈值电压，而另一晶体管被抗蚀剂掩模覆盖。因此，所需抗蚀剂掩模中的注入物种的原子量减少，从而便于除去抗蚀剂掩模。此外，与常规制造工艺相比，植入步骤的数量减少。

67. 发明申请

US20140167110A1 PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION 审中-公开
标题翻译：部分多用途通道预防措施
公开(公告)号：US20140167110A1
公开(公告)日：2014-06-19
申请号：US14188022
申请日：2014-02-24
申请人： GLOBAL FOUNDRIES Inc.
发明人： Peter JAVORKA , Glyn BRAITHWAITE
IPC分类号： H01L29/78 , H01L27/092 , H01L29/49
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28052 , H01L21/823814 , H01L21/823828 , H01L27/092 , H01L29/4933 , H01L29/66507 , H01L29/66583 , H01L29/78
摘要： Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
摘要翻译：半导体器件在栅极和源极/漏极区域中形成没有拉链缺陷或沟槽和贯穿植入以及不同的硅化物厚度，实施例包括在衬底上形成栅极，在栅极上形成氮化物帽，形成源极/漏极区域在栅极的每一侧的衬底中，在栅极的每一侧上的源极/漏极区域上形成湿盖填充层，从栅极去除氮化物帽，并在栅极的顶部部分形成非晶化层。实施例包括通过注入低能离子形成非晶化层。

68. 发明授权

US08212346B2 Method and apparatus for reducing semiconductor package tensile stress 有权
标题翻译：降低半导体封装拉伸应力的方法和装置
公开(公告)号：US08212346B2
公开(公告)日：2012-07-03
申请号：US12259357
申请日：2008-10-28
申请人： E. Todd Ryan , Holger Schuehrer , Seung-Hyun Rhee
发明人： E. Todd Ryan , Holger Schuehrer , Seung-Hyun Rhee
IPC分类号： H01L23/06
CPC分类号： H01L23/562 , H01L23/3121 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.
摘要翻译：提供具有降低的拉伸应力的半导体封装。半导体封装包括封装衬底和半导体管芯。半导体管芯电耦合和物理耦合到封装衬底并且包括并入其中的应力消除层。应力消除层在半导体管芯内具有预定的结构和预定位置，用于在半导体封装的加热和冷却期间减小半导体封装的拉伸应力。

69. 发明申请

US20120153402A1 EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS BY APPLYING A UNIFORM OXIDE LAYER PRIOR TO CAVITY ETCHING 有权
标题翻译：通过在空洞蚀刻前应用均匀的氧化物层在晶体管中形成的嵌入式SIGMA-形状的半导体合金
公开(公告)号：US20120153402A1
公开(公告)日：2012-06-21
申请号：US13238180
申请日：2011-09-21
申请人： Stephan Kronholz , Andreas Ott , Ina Ostermay
发明人： Stephan Kronholz , Andreas Ott , Ina Ostermay
IPC分类号： H01L27/088 , H01L21/66
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L22/12
摘要： When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.
摘要翻译：当形成需要嵌入式半导体合金的复杂晶体管时，可以通过提供均匀的氧化物层来在例如晶体学各向异性蚀刻步骤的基础上形成具有优异均匀性的空腔，以便减少与工艺相关的波动或排队时间变化。可以基于APC控制方式形成均匀的氧化物层。

70. 发明授权

US08062952B2 Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors 有权
标题翻译：双向应变SOI衬底中的应变变换用于P沟道和N沟道晶体管的性能增强
公开(公告)号：US08062952B2
公开(公告)日：2011-11-22
申请号：US12784819
申请日：2010-05-21
申请人： Jan Hoentschel , Stefan Flachowsky , Andy Wei
发明人： Jan Hoentschel , Stefan Flachowsky , Andy Wei
IPC分类号： H01L21/30
CPC分类号： H01L27/1203 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7842 , H01L29/7846
摘要： In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.
摘要翻译：在先进的SOI器件中，可以在全局应变半导体层的基础上实现高拉伸应变分量，同时通过适当地选择高度 - 长度方面，可以在P沟道晶体管中产生一定的压缩应变相应活性区的比例。已经认识到，有效区域中最终获得的应变分布强烈地取决于有源区的纵横比。因此，通过为N沟道晶体管选择中等的高度 - 长度长宽比，可以保留初始拉伸应变分量的很大一部分。另一方面，用于P沟道晶体管的中等高度的长宽比可能导致有源区的中心表面区域中的压缩应变分量。

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