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61. 发明授权

US06365466B1 Dual gate process using self-assembled molecular layer 有权
标题翻译：双栅工艺采用自组装分子层
公开(公告)号：US06365466B1
公开(公告)日：2002-04-02
申请号：US09774939
申请日：2001-01-31
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L21336
CPC分类号： B82Y30/00 , B82Y10/00 , H01L21/32139 , H01L21/823842
摘要： A method of forming dual gate structures on first and second portions, substrate includes: providing an insulative layer over the substrate; providing a first layer of material having a first work function with the first portion of the substrate; providing a second layer of material having a second work function different than the first work function over the second portion of the substrate; patterning a third layer of material over the first and second layers of material, whereby features of the third layer of material are provided over both the first and second portions of the substrate; providing a self-assembled molecular layer over at least a portion of the features, wherein the self-assembled molecular layer has regions of etch selectivity; and etching the self-assembled molecular layer at the regions of etch selectivity until gate structures are formed over the first and second portions of the substrate.
摘要翻译：在第一和第二部分上形成双栅极结构的方法，衬底包括：在衬底上提供绝缘层; 提供具有第一功函数的第一层材料与基底的第一部分; 在所述基板的第二部分上提供具有与所述第一功函数不同的第二功函数的第二层材料; 在第一和第二层材料上图案化第三层材料，由此在衬底的第一和第二部分上提供第三层材料的特征; 在特征的至少一部分上提供自组装分子层，其中所述自组装分子层具有蚀刻选择性的区域; 以及在蚀刻选择性区域刻蚀自组装分子层，直到在该衬底的第一和第二部分上形成栅极结构。

62. 发明授权

US06320236B1 Optimization of logic gates with criss-cross implants to form asymmetric channel regions 失效
标题翻译：优化具有十字交叉植入物的逻辑门以形成不对称沟道区域
公开(公告)号：US06320236B1
公开(公告)日：2001-11-20
申请号：US09413737
申请日：1999-10-06
申请人： Zoran Krivokapic , Ognjen Milic
发明人： Zoran Krivokapic , Ognjen Milic
IPC分类号： H01L2976
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823412
摘要： An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack. Adjacent gate stacks can have asymmetric channels with the same dopant concentration, or may be fabricated having different concentrations by varying the height of the photoresist mask to achieve a wider ion-implantation beam and thus form a higher dopant concentration on the target channel region. The optimized gates with higher dopant concentration improves off-state leakage current (10−8 amps/micron), but reduce the gate speed. The gates may also be optimized for gate speed and power consumption by producing uniformly doped asymmetric gates (20-50 pico-second fall time delays being achievable).
摘要翻译：公开了一种具有优化的非对称沟道区域的集成半导体逻辑门装置及其制造方法。制造工艺包括离子注入通道的漏极侧，通过使用十字交叉形式的离子注入在栅极晶体管上产生非对称沟道。十字交叉离子注入在形成多个栅极堆叠之后进行，并且通过图案化的光致抗蚀剂掩模来实现，该图案化的光刻胶掩模在相邻的栅极堆叠之上留下开放的未受保护的区域，通过其进行离子注入。十字交叉离子注入包括由影响光致抗蚀剂掩模的高度的切线确定的两个倾斜角，栅极堆叠对上的未保护开口的宽度和沟道区域的宽度，包括与源极/漏极势垒在覆盖栅极堆叠下方最小的点。相邻的栅极堆叠可以具有相同的掺杂剂浓度的不对称沟道，或者可以通过改变光致抗蚀剂掩模的高度来制造具有不同的浓度，以实现较宽的离子注入束并因此在目标沟道区上形成更高的掺杂剂浓度。具有较高掺杂浓度的优化栅极可提高截止状态下的漏电流（10-8安培/微米），但降低栅极速度。也可以通过产生均匀掺杂的非对称栅极（20-50微微秒的下降时间延迟可实现）来对栅极速度和功耗进行优化。

63. 发明授权

US06294412B1 Silicon based lateral tunneling memory cell 有权
标题翻译：基于硅的横向隧道存储单元
公开(公告)号：US06294412B1
公开(公告)日：2001-09-25
申请号：US09591382
申请日：2000-06-09
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L2100
CPC分类号： B82Y10/00 , H01L27/11 , H01L27/1203 , Y10S438/979
摘要： An SRAM memory cell device is provide having a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 Å thick, allowing for increased memory cell density over a given area. The RTD latch structure is a lateral RTD device, such that the outer contacting regions, the tunneling barriers and the central quantum well are formed side-by-side as opposed to being stacked on top of one another. This allows for formation of the memory cell device on very thin silicon layers. The layers can then be stacked to form memory devices for use with computers and the like. The memory device can be formed employing silicon-on-insulator (SOI) technology to take advantage of SOI device characteristics.
摘要翻译：提供具有单个晶体管和单个RTD锁存器结构的SRAM存储器单元器件。单个晶体管和RTD锁存结构形成在非常薄的硅层上，通常在250至大约厚的范围内，允许在给定区域上增加存储单元密度。 RTD闩锁结构是横向RTD装置，使得外部接触区域，隧道势垒和中心量子阱彼此并排地形成，而不是彼此堆叠。这允许在非常薄的硅层上形成存储单元器件。然后可以堆叠层以形成用于计算机等的存储器件。可以使用绝缘体上硅（SOI）技术形成存储器件以利用SOI器件特性。

64. 发明授权

US06246096B1 Totally self-aligned transistor with tungsten gate 失效
标题翻译：具有钨栅的全自对准晶体管
公开(公告)号：US06246096B1
公开(公告)日：2001-06-12
申请号：US09103388
申请日：1998-06-24
申请人： Zoran Krivokapic , Ognjen Milic
发明人： Zoran Krivokapic , Ognjen Milic
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/26586 , H01L21/28079 , H01L29/1045 , H01L29/41775 , H01L29/66492 , H01L29/66583
摘要： A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.
摘要翻译：具有钨栅的全自对准晶体管。单个掩模用于对准源极，漏极，栅极和隔离区域。通过对这些区域使用单个掩码，覆盖误差大大降低。中间间隙电极也与晶体管自对准。电极优选由钨金属形成。

65. 发明授权

US06087208A Method for increasing gate capacitance by using both high and low dielectric gate material 失效
标题翻译：通过使用高介电栅极材料和低介电栅极材料来增加栅极电容的方法
公开(公告)号：US06087208A
公开(公告)日：2000-07-11
申请号：US52386
申请日：1998-03-31
申请人： Zoran Krivokapic , Srinath Krishnan , Geoffrey Choh-Fei Yeap , Matthew Buynoski
发明人： Zoran Krivokapic , Srinath Krishnan , Geoffrey Choh-Fei Yeap , Matthew Buynoski
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/60
CPC分类号： H01L21/28194 , H01L21/26506 , H01L29/4983 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/42376
摘要： A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.
摘要翻译：提供了一种用于制造MOSFET器件的方法。该方法包括使包含第一和第二栅极氧化物材料的栅极氧化物化的步骤。第一栅极氧化物材料具有比第二栅极氧化物材料更高的介电常数。第一栅极氧化物材料形成为在器件的源极/漏极延伸区域之上; 并且第二栅极氧化物材料形成在器件的沟道区域上。第一栅极氧化物材料具有低介电常数并且用于减轻栅极边缘场效应。第二栅极氧化物材料具有高介电常数并且提供用于在器件的沟道区域上形成厚栅极氧化物。第二栅极氧化物材料的受控均匀生长由于其厚度而容易。

66. 发明授权

US6025235A Short channel transistor having resistive gate extensions 失效
公开(公告)号：US6025235A
公开(公告)日：2000-02-15
申请号：US37488
申请日：1998-03-10
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/762 , H01L21/768 , H01L29/423 , H01L21/334 , H01L21/335 , H01L21/38
CPC分类号： H01L29/41783 , H01L21/28114 , H01L21/76224 , H01L21/76895 , H01L29/42316 , H01L29/42376 , H01L29/66537 , H01L29/66553 , H01L29/6656 , H01L29/66575 , H01L21/2257 , H01L29/665 , H01L29/66545
摘要： A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided. In one aspect, the invention comprises: forming a transistor region on a silicon substrate, the region including a first and second spacers on a first side and a second side of the region, respectively, the spacers overlying a first oxide layer on the surface of the substrate; etching the first oxide layer leaving a first and second gaps between the first and second spacers, respectively, and the silicon substrate; forming a gate oxide layer overlying the surface of the substrate in the transistor region, the gate oxide having a thickness; and filling the transistor region with polysilicon to cover the gate oxide region.

67. 发明授权

US5879998A Adaptively controlled, self-aligned, short channel device and method for manufacturing same 失效
标题翻译：自适应控制，自对准，短通道装置及其制造方法
公开(公告)号：US5879998A
公开(公告)日：1999-03-09
申请号：US890388
申请日：1997-07-09
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L21/768 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423
CPC分类号： H01L29/66553 , H01L21/28114 , H01L21/28123 , H01L21/76224 , H01L21/76895 , H01L29/0847 , H01L29/1083 , H01L29/41775 , H01L29/41783 , H01L29/42376 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/665 , H01L29/66537
摘要： A short channel semiconductor device having source and drain regions in a substrate and a gate region on the top surface of the substrate between the source and drain regions is disclosed. In one embodiment, the method comprises: forming a device area in the silicon by forming a pattern stack, and forming pattern spacers adjacent to the pattern stack; forming a trench isolation about the pattern stack; removing the pattern spacers; depositing an epitaxial layer over the trench oxide and adjacent to the pattern stack; removing the pattern stack; and forming adaptively controlled spacers in the region to control said short channel length of the device.The apparatus of the present invention comprises: a semiconductor substrate; a source region and a drain region formed in the substrate; a gate region, comprising a first and a second oxide regions, a first control spacer and a second control spacer positioned above the substrate and adjacent to the first and second oxide regions, respectively, and a polysilicon layer positioned between the spacers; and an epitaxial layer, adjacent to the source and drain region and surrounding said first and second spacers.
摘要翻译：公开了一种短沟道半导体器件，其在衬底中具有源极和漏极区域以及在源极和漏极区域之间的衬底顶表面上的栅极区域。在一个实施例中，该方法包括：通过形成图案叠层在硅中形成器件区域，以及形成邻近图案层叠的图案间隔物; 围绕图案堆叠形成沟槽隔离; 去除图案间隔物; 在所述沟槽氧化物上沉积外延层并且邻近所述图案层叠; 去除图案堆栈; 以及在所述区域中形成自适应控制的间隔物以控制所述装置的所述短通道长度。本发明的装置包括：半导体衬底; 形成在所述基板中的源极区域和漏极区域; 包括第一和第二氧化物区域的栅极区域，分别位于衬底上方并分别邻近第一和第二氧化物区域的第一控制间隔物和第二控制间隔物以及位于间隔物之间的多晶硅层; 以及与源极和漏极区相邻并且围绕所述第一和第二间隔物的外延层。

68. 发明授权

US5601954A Attenuated phase shift mask comprising phase shifting layer with parabolically shaped sidewalls 失效
标题翻译：衰减的相移掩模包括具有抛物线形侧壁的相移层
公开(公告)号：US5601954A
公开(公告)日：1997-02-11
申请号：US469148
申请日：1995-06-05
申请人： Zoran Krivokapic , Christopher A. Spence
发明人： Zoran Krivokapic , Christopher A. Spence
IPC分类号： G03F1/32 , H01L21/027 , G03F9/00
CPC分类号： G03F1/32
摘要： An attenuated phase shift mask comprises a first layer having a thickness to provide a transmission in the range of about 3 to 10% formed on a transparent substrate and a second layer comprising a transparent material having a thickness to provide a desired phase shift, formed on said first layer. For a phase shift of 180.degree. and i-line wavelength (365 nm), where chromium is used as the first layer, then a thickness within the range of about 25 to 75 run is employed; where silicon dioxide is used as the second layer, then a thickness of about 400 to 450 nm is employed. While the oxide may be dry-etched, an isotropic wet etch provides superior aerial images.
摘要翻译：衰减相移掩模包括第一层，其具有提供在透明衬底上形成的大约3至10％范围内的透射率的厚度，以及包括具有提供期望相移的厚度的透明材料的第二层，形成在说第一层。对于使用铬作为第一层的180度和i线波长（365nm）的相移，则使用在约25至75nm范围内的厚度; 其中使用二氧化硅作为第二层，然后使用约400至450nm的厚度。虽然氧化物可以被干蚀刻，但是各向同性的湿蚀刻提供了优异的航空图像。

69. 发明授权

US5556525A PVD sputter system having nonplanar target configuration and methods for operating same 失效
标题翻译：具有非平面目标配置的PVD溅射系统及其操作方法
公开(公告)号：US5556525A
公开(公告)日：1996-09-17
申请号：US316090
申请日：1994-09-30
申请人： Zoran Krivokapic , David S. Bang
发明人： Zoran Krivokapic , David S. Bang
IPC分类号： C23C14/34
CPC分类号： C23C14/3407
摘要： A PVD sputter system having a nonplanar target surface is disclosed. The configuration of the nonplanar target surface is adjusted to provide improved uniformity in deposition film thickness and step coverage at the peripheral boundary regions of the substrate. Emission-inducing power is distributed independently to different portions of the nonplanar target surface so as to modify the deposition profile according to substrate size and other factors.
摘要翻译：公开了一种具有非平面靶表面的PVD溅射系统。调整非平面目标表面的配置，以提供在衬底的周边边界区域的沉积膜厚度和台阶覆盖率的改善的均匀性。发射诱导功率独立地分布到非平面目标表面的不同部分，以便根据衬底尺寸和其他因素改变沉积轮廓。

70. 发明申请

US20120038051A1 BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME 有权
标题翻译：带硅胶的局部连接器和其制造方法
公开(公告)号：US20120038051A1
公开(公告)日：2012-02-16
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

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