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61. 发明授权

US07230477B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07230477B2
公开(公告)日：2007-06-12
申请号：US11296442
申请日：2005-12-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yohihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yohihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L2/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO 1〜MIO 4）通常用于连接电路块。

62. 发明授权

US07199639B2 Semiconductor device with level converter having signal-level shifting block and signal-level determination block 有权
标题翻译：具有电平转换器的半导体器件具有信号电平移位块和信号电平确定块
公开(公告)号：US07199639B2
公开(公告)日：2007-04-03
申请号：US11410956
申请日：2006-04-26
申请人： Yusuke Kanno , Hiroyuki Mizuno , Takeshi Sakata , Takao Watanabe
发明人： Yusuke Kanno , Hiroyuki Mizuno , Takeshi Sakata , Takao Watanabe
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H03K19/018521
摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.
摘要翻译：公开了一种包括电平转换器（LSC）的半导体器件。电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2）电源（VDDQ）。升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC）自动控制防泄漏，外接控制信号。

63. 发明授权

US06990002B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06990002B2
公开(公告)日：2006-01-24
申请号：US10751402
申请日：2004-01-06
申请人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果。在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

64. 发明申请

US20050099876A1 Semiconductor integrated circuit and data processing system 失效
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US20050099876A1
公开(公告)日：2005-05-12
申请号：US11010324
申请日：2004-12-14
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F12/08 , G11C7/06 , G11C7/10 , G11C11/401 , G11C11/4091 , G11C11/4093 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
摘要翻译：为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。数据保存在每个存储体的读出放大器中。当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。即，使每个存储体用作读出放大器高速缓存。为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据地址由另一个存储体中的读出放大器预读。

65. 发明授权

US06847578B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US06847578B2
公开(公告)日：2005-01-25
申请号：US10729934
申请日：2003-12-09
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F12/08 , G11C7/06 , G11C7/10 , G11C11/401 , G11C11/4091 , G11C11/4093 , G11C7/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

66. 发明授权

US06708249B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US06708249B2
公开(公告)日：2004-03-16
申请号：US10101063
申请日：2002-03-20
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

67. 发明授权

US06653868B2 Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit 有权
公开(公告)号：US06653868B2
公开(公告)日：2003-11-25
申请号：US10173035
申请日：2002-06-18
申请人： Nobuhiro Oodaira , Hiroyuki Mizuno , Yusuke Kanno , Koichiro Ishibashi , Masanao Yamaoka
发明人： Nobuhiro Oodaira , Hiroyuki Mizuno , Yusuke Kanno , Koichiro Ishibashi , Masanao Yamaoka
IPC分类号： H03K19094
CPC分类号： G06F17/505 , H01L27/1203
摘要： A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

68. 发明授权

US06285626B1 Semiconductor device 有权
公开(公告)号：US06285626B1
公开(公告)日：2001-09-04
申请号：US09730785
申请日：2000-12-07
申请人： Hiroyuki Mizuno , Yusuke Kanno , Takao Watanabe
发明人： Hiroyuki Mizuno , Yusuke Kanno , Takao Watanabe
IPC分类号： G11C800
摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

69. 发明授权

US09151630B2 Evaluation indication system, evaluation indication method and computer-readable storage medium 有权
标题翻译：评价指标体系，评价指标法和计算机可读存储介质
公开(公告)号：US09151630B2
公开(公告)日：2015-10-06
申请号：US13523193
申请日：2012-06-14
申请人： Naoki Miura , Junichi Nonomura , Junki Yamakawa , Hiroyuki Mizuno
发明人： Naoki Miura , Junichi Nonomura , Junki Yamakawa , Hiroyuki Mizuno
IPC分类号： G06F19/00 , G06G7/70 , G01C21/34
CPC分类号： G01C21/3469 , B60K2350/1092 , Y02T10/84
摘要： Evaluation indication systems, methods, and programs display a current position of a vehicle and a map around the current position on a display unit, acquire current evaluations that indicate evaluations of fuel consumption in current travel of the vehicle by unit sections, and acquire previous evaluations that indicate evaluations of fuel consumption of the vehicle in a past prior to the current travel by unit sections. The systems, methods, and programs indicate the current evaluations and the previous evaluations together by unit sections on the map.
摘要翻译：评估指示系统，方法和程序在显示单元上显示车辆的当前位置和当前位置周围的地图，获取指示车辆按单元部分的当前行驶中的燃料消耗的评估的当前评估，并且获取先前的评估这表示在单位部门当前旅行之前过去的车辆燃料消耗的评估。系统，方法和程序通过地图上的单位部分一起显示当前的评估和以前的评估。

70. 发明授权

US08674745B2 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit 有权
标题翻译：电平转换电路和采用电平转换电路的半导体集成电路器件
公开(公告)号：US08674745B2
公开(公告)日：2014-03-18
申请号：US13406715
申请日：2012-02-28
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
摘要翻译：在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。在升高电路中，提供逻辑运算功能。

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