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61. 发明授权

US06300807B1 Timing-control circuit device and clock distribution system 有权
标题翻译：定时控制电路设备和时钟分配系统
公开(公告)号：US06300807B1
公开(公告)日：2001-10-09
申请号：US09388438
申请日：1999-09-02
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Takeshi Sakata , Satoru Hanzawa , Hiroyuki Mizuno , Kiyoshi Hasegawa , Masaru Kokubo , Hirokazu Aoki
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Takeshi Sakata , Satoru Hanzawa , Hiroyuki Mizuno , Kiyoshi Hasegawa , Masaru Kokubo , Hirokazu Aoki
IPC分类号： H03L706
CPC分类号： H04L7/0008 , G06F1/10 , H03K5/135 , H04L7/0037
摘要： A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
摘要翻译：使用同步镜延迟电路的定时控制电路装置即使在负载变化时也保持时钟信号同步。参考时钟信号（clkin 11）被输入到定时控制电路（SMDF 14），用于产生内部时钟（dclk12），然后通过缓冲器（BUF 15）产生外部时钟（clkout 13）。外部时钟信号被反馈到定时控制电路（SMDF14），用于产生内部时钟信号，以使外部时钟信号与参考时钟信号同相。定时控制电路设置有用于检测内部时钟信号和外部时钟信号之间的相位差的电路（FDA 21，MCC 22）以及用于控制延迟时间的延迟电路（DCL 24），因此延迟电路（DCL24）可以根据检测到的相位差来改变延迟时间。

62. 发明授权

US08799560B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08799560B2
公开(公告)日：2014-08-05
申请号：US13389260
申请日：2010-06-18
申请人： Satoru Hanzawa
发明人： Satoru Hanzawa
IPC分类号： G06F12/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097
摘要： A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period.
摘要翻译：实现了高速大容量相变存储器。根据本发明的半导体器件包括：多个存储器平面MP; 与多个存储器平面配对的多个存储信息寄存器组SDRBK; 和芯片控制电路CPCTL。多个存储器平面包括多个存储单元。此外，多个存储信息寄存器组临时保留要存储在多个存储器平面中的信息。此外，芯片控制电路包括临时存储指示存储信息的卷的值的寄存器，并且第一存储信息量小于第二存储信息量。当第一存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第一时段期间被激活。当第二存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第二时段期间被激活。通过这种结构，第一周期比第二周期短。

63. 发明授权

US08482997B2 Method of manufacturing non-volatile memory module 有权
标题翻译：制造非易失性存储器模块的方法
公开(公告)号：US08482997B2
公开(公告)日：2013-07-09
申请号：US13366329
申请日：2012-02-05
申请人： Satoru Hanzawa , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Saen
发明人： Satoru Hanzawa , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Saen
IPC分类号： G11C7/00 , G11C11/00 , H01L21/00
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译：实现了高度可靠的大容量相变存储器模块。根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件其中所选择的存储器单元被定位。根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件）电路和电流镜电路。

64. 发明授权

US08248843B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08248843B2
公开(公告)日：2012-08-21
申请号：US12986178
申请日：2011-01-07
申请人： Satoru Hanzawa , Yoshikazu Iida
发明人： Satoru Hanzawa , Yoshikazu Iida
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C2213/79
摘要： In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.
摘要翻译：在包括具有可变电阻的存储器件RQ和选择晶体管MQ的存储单元MC的存储器阵列MCA中，目的是在短时间内接收固定量的存储数据，并且实现对存储单元，具有抑制的峰值电流。为了实现该目的，通过使用多个读出放大器和临时存储存储数据来缩短重写操作中的数据总线占用时间，并且使用具有不同相位的控制信号来提供和激活多个编程电路。通过上述，可以实现具有低电流消耗的相变存储器系统，而不会降低数据总线的利用率。

65. 发明申请

US20120134203A1 Semiconductor Device and Data Processing System 有权
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20120134203A1
公开(公告)日：2012-05-31
申请号：US13300139
申请日：2011-11-18
申请人： Seiji Miura , Satoru Hanzawa
发明人： Seiji Miura , Satoru Hanzawa
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C13/0007 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2211/5623
摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.
摘要翻译：在相变存储器中，当写入M位（8位= 1字节）数据时，以n位（M> n）数据为单位执行擦除操作和编程操作。此外，当写入M位数据时，以n位（M> n）数据为单位执行编程操作。此外，当从存储单元读取M位数据时，以n位（M> n）数据为单位执行读操作。例如，当数据被写入相变存储器时，数据不被重写，而是在擦除目标存储单元之后执行程序。擦除的数据大小和程序的数据大小相等。擦除和编程操作仅针对所需的数据大小执行。

66. 发明申请

US20100061132A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20100061132A1
公开(公告)日：2010-03-11
申请号：US12516690
申请日：2006-12-07
申请人： Yoshihisa Fujisaki , Satoru Hanzawa , Kenzo Kurotsuchi , Nozomu Matsuzaki , Norikatsu Takaura
发明人： Yoshihisa Fujisaki , Satoru Hanzawa , Kenzo Kurotsuchi , Nozomu Matsuzaki , Norikatsu Takaura
IPC分类号： G11C11/00 , H01L45/00 , G11C5/02 , G11C7/00
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0069 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233
摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.
摘要翻译：在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103，设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

67. 发明授权

US07542347B2 Semiconductor device 有权
公开(公告)号：US07542347B2
公开(公告)日：2009-06-02
申请号：US11873254
申请日：2007-10-16
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C16/04
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

68. 发明授权

US07489588B2 Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation 失效
标题翻译：具有在突发读取操作中配备有电流控制电路的主放大器的半导体存储器件
公开(公告)号：US07489588B2
公开(公告)日：2009-02-10
申请号：US11924353
申请日：2007-10-25
申请人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
IPC分类号： G11C7/08
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译：提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小读周期。因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

69. 发明申请

US20080121860A1 Semiconductor memory cell and method of forming same 审中-公开
标题翻译：半导体存储单元及其形成方法
公开(公告)号：US20080121860A1
公开(公告)日：2008-05-29
申请号：US12007851
申请日：2008-01-16
申请人： Hideyuki Matsuoka , Kiyoo Itoh , Motoyasu Terao , Satoru Hanzawa , Takeshi Sakata
发明人： Hideyuki Matsuoka , Kiyoo Itoh , Motoyasu Terao , Satoru Hanzawa , Takeshi Sakata
IPC分类号： H01L29/66 , G11C11/00
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
摘要翻译：半导体存储单元及其形成方法利用垂直选择晶体管来消除利用相位变化的现有技术的存储单元中的大的单元表面积的问题。通过本发明实现了具有比现有技术的DRAM器件更小的表面积的存储单元。除了读取操作中的低功耗之外，本发明还提供即使在写入操作期间具有低功耗的相变存储器。相变存储器也具有稳定的读出操作。

70. 发明授权

US07324372B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07324372B2
公开(公告)日：2008-01-29
申请号：US11507576
申请日：2006-08-22
申请人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
发明人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译：本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管进行。为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

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