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61. 发明授权

US07778072B2 Method for fabricating charge-trapping memory 有权
标题翻译：电荷捕获存储器的制造方法
公开(公告)号：US07778072B2
公开(公告)日：2010-08-17
申请号：US11460497
申请日：2006-07-27
申请人： Yen-Hao Shih , Jung-Yu Hsieh , Yi-Lin Yang , Chia-Hua Chang , Jenn-Gwo Hwu
发明人： Yen-Hao Shih , Jung-Yu Hsieh , Yi-Lin Yang , Chia-Hua Chang , Jenn-Gwo Hwu
IPC分类号： G11C11/34
CPC分类号： H01L21/76838 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the device fabrication process. The annealing process is conducted at a temperature of about 350° C. to 450° C. and with the concentration of the hydrogen gas greater than 0.5 mole percent.
摘要翻译：提供了一种电荷俘获存储器件的制造方法。该方法包括形成至少具有电荷捕获介质的堆叠结构。然后在器件制造过程之后对堆叠结构进行氢气中的退火处理。退火过程在约350℃至450℃的温度下进行，氢气的浓度大于0.5摩尔％。

62. 发明申请

US20070293006A1 METHOD FOR FABRICATING A CHARG TRAPPING MEMORY DEVICE 有权
标题翻译：一种用于制作电荷捕捉存储器件的方法
公开(公告)号：US20070293006A1
公开(公告)日：2007-12-20
申请号：US11425160
申请日：2006-06-20
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

63. 发明授权

US07863132B2 Method for fabricating a charge trapping memory device 有权
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US07863132B2
公开(公告)日：2011-01-04
申请号：US11425160
申请日：2006-06-20
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

64. 发明申请

US20110073937A1 Method for Fabricating a Charge Trapping Memory Device 有权
标题翻译：制造电荷俘获存储器件的方法
公开(公告)号：US20110073937A1
公开(公告)日：2011-03-31
申请号：US12962361
申请日：2010-12-07
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

65. 发明申请

US20080164513A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非挥发性半导体存储器件以及制造非易失性半导体存储器件的方法
公开(公告)号：US20080164513A1
公开(公告)日：2008-07-10
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lal , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lal , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

66. 发明授权

US07824991B2 Method for nitridation of the interface between a dielectric and a substrate in a MOS device 有权
标题翻译：在MOS器件中电介质和衬底之间的界面氮化的方法
公开(公告)号：US07824991B2
公开(公告)日：2010-11-02
申请号：US11334249
申请日：2006-01-18
申请人： Yen-Hao Shih , Shih-Chin Lee
发明人： Yen-Hao Shih , Shih-Chin Lee
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L21/28282 , H01L29/517 , H01L29/518 , Y10S438/954
摘要： A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.
摘要翻译： MOSFET制造工艺包括电介质硅界面的氮化，使得硅 - 悬挂键与氮原子连接，产生比硅 - 氢键更强的硅 - 氮键。在基板上形成隧道电介质。然后在隧道介电层上形成氮化物层。然后将氮化物层的顶部转化为氧化物，并且衬底和隧道电介质之间的界面同时氮化氮化物层与氧化物的氮化。

67. 发明授权

US07314815B2 Manufacturing method of one-time programmable read only memory 有权
标题翻译：一次性可编程只读存储器的制造方法
公开(公告)号：US07314815B2
公开(公告)日：2008-01-01
申请号：US11308550
申请日：2006-04-06
申请人： Chia-Hua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
发明人： Chia-Hua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
IPC分类号： H01L21/336 , H01L21/326 , H01L21/479 , H01L21/44
CPC分类号： H01L27/101 , G11C17/16 , H01L27/1021
摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.
摘要翻译：提供一次性可编程只读存储器。顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。导电层设置在P型半导体衬底上。导电层还具有与第一P型掺杂层交叉的线性结构。第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。在导电层和第一N型掺杂层之间设置反熔丝层。

68. 发明申请

US20070166923A1 Method for nitridation of the interface between a dielectric and a substrate in a MOS device 有权
标题翻译：在MOS器件中电介质和衬底之间的界面氮化的方法
公开(公告)号：US20070166923A1
公开(公告)日：2007-07-19
申请号：US11334249
申请日：2006-01-18
申请人： Yen-Hao Shih , Shih-Chin Lee
发明人： Yen-Hao Shih , Shih-Chin Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/517 , H01L29/518 , Y10S438/954
摘要： A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon-nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.
摘要翻译： MOSFET制造工艺包括电介质硅界面的氮化，使得硅 - 悬挂键与氮原子连接，产生比硅 - 氢键更强的硅 - 氮键。在基板上形成隧道电介质。然后在隧道介电层上形成氮化物层。然后将氮化物层的顶部转化为氧化物，并且衬底和隧道电介质之间的界面同时氮化氮化物层与氧化物的氮化。

69. 发明授权

US07053406B1 One-time programmable read only memory and manufacturing method thereof 有权
标题翻译：一次性可编程只读存储器及其制造方法
公开(公告)号：US07053406B1
公开(公告)日：2006-05-30
申请号：US10907442
申请日：2005-04-01
申请人： ChiaHua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
发明人： ChiaHua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.
摘要翻译：提供一次性可编程只读存储器。顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。导电层设置在P型半导体衬底上。导电层还具有与第一P型掺杂层交叉的线性结构。第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。在导电层和第一N型掺杂层之间设置反熔丝层。

70. 发明申请

US20060199361A1 MANUFACTURING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY 有权
标题翻译：一次性编程只读存储器的制造方法
公开(公告)号：US20060199361A1
公开(公告)日：2006-09-07
申请号：US11308550
申请日：2006-04-06
申请人： Chia-Hua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
发明人： Chia-Hua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
IPC分类号： G11C17/00 , H01L21/44
CPC分类号： H01L27/101 , G11C17/16 , H01L27/1021
摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.
摘要翻译：提供一次性可编程只读存储器。顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。导电层设置在P型半导体衬底上。导电层还具有与第一P型掺杂层交叉的线性结构。第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。在导电层和第一N型掺杂层之间设置反熔丝层。

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