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61. 发明申请

US20060043459A1 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
公开(公告)号：US20060043459A1
公开(公告)日：2006-03-02
申请号：US10934246
申请日：2004-09-02
申请人： Bomy Chen , Sohrab Kianian , Yaw Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Hu
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

62. 发明申请

US20050239284A1 WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE 审中-公开
标题翻译：具有降低入口电容的集成电路接线结构
公开(公告)号：US20050239284A1
公开(公告)日：2005-10-27
申请号：US10709204
申请日：2004-04-21
申请人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
发明人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

63. 发明授权

US06861315B1 Method of manufacturing an array of bi-directional nonvolatile memory cells 有权
标题翻译：制造双向非易失性存储单元阵列的方法
公开(公告)号：US06861315B1
公开(公告)日：2005-03-01
申请号：US10641432
申请日：2003-08-14
申请人： Bomy Chen , Sohrab Kianian
发明人： Bomy Chen , Sohrab Kianian
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction. The layer of word region is cut into a plurality of strips in the second direction to form a plurality of spaced apart word lines. Each strip is spaced apart from one another and substantially parallel to one another, and cuts through the floating gate in each of the trenches. Electrical connections are made to each of the region of second conductivity type and each of the plurality of spaced apart word lines.
摘要翻译：一种制造基本上单晶半导体材料的衬底中的双向非易失性存储单元的阵列的方法，其中所述材料具有第一导电类型，所述衬底具有基本平坦的表面，包括形成多个间隔开的在平面表面上沿第一方向大致平行的沟槽。每个沟槽都有一个侧壁和一个底部。在每个沟槽的底部形成第二导电类型的区域。在每个沟槽中形成浮动栅极，其与沟槽的侧壁绝缘并间隔开。浮动门具有靠近底部的第一端和离底部最远的第二端。围绕每个浮动栅极的第二端形成隧穿氧化物层。在隧道氧化物层上形成一个字区域层。单词区域的层在基本上垂直于第一方向的第二方向上延伸。字区域在第二方向被切成多个条带以形成多个间隔开的字线。每个条带彼此间隔开并且基本上彼此平行，并且穿过每个沟槽中的浮动栅极。对第二导电类型的区域和多个间隔开的字线中的每一个进行电连接。

64. 发明申请

US20050037576A1 METHOD OF MANUFACTURING AN ARRAY OF BI-DIRECTIONAL NONVOLATILE MEMORY CELLS 有权
标题翻译：制作双向非线性记忆细胞阵列的方法
公开(公告)号：US20050037576A1
公开(公告)日：2005-02-17
申请号：US10641432
申请日：2003-08-14
申请人： Bomy Chen , Sohrab Kianian
发明人： Bomy Chen , Sohrab Kianian
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction. The layer of word region is cut into a plurality of strips in the second direction to form a plurality of spaced apart word lines. Each strip is spaced apart from one another and substantially parallel to one another, and cuts through the floating gate in each of the trenches. Electrical connections are made to each of the region of second conductivity type and each of the plurality of spaced apart word lines.
摘要翻译：一种制造基本上单晶半导体材料的衬底中的双向非易失性存储单元的阵列的方法，其中所述材料具有第一导电类型，所述衬底具有基本平坦的表面，包括形成多个间隔开的在平面表面上沿第一方向大致平行的沟槽。每个沟槽都有一个侧壁和一个底部。在每个沟槽的底部形成第二导电类型的区域。在每个沟槽中形成浮动栅极，其与沟槽的侧壁绝缘并间隔开。浮动门具有靠近底部的第一端和离底部最远的第二端。围绕每个浮动栅极的第二端形成隧穿氧化物层。在隧道氧化物层上形成一个字区域层。单词区域的层在基本上垂直于第一方向的第二方向上延伸。字区域在第二方向被切成多个条带以形成多个间隔开的字线。每个条带彼此间隔开并且基本上彼此平行，并且穿过每个沟槽中的浮动栅极。对第二导电类型的区域和多个间隔开的字线中的每一个进行电连接。

65. 发明申请

US20050035414A1 MULTI-BIT ROM CELL WITH BI-DIRECTIONAL READ AND A METHOD FOR MAKING THEREOF 有权
标题翻译：具有双向读取的多位单元ROM单元及其制造方法
公开(公告)号：US20050035414A1
公开(公告)日：2005-02-17
申请号：US10642077
申请日：2003-08-14
申请人： Bomy Chen , Kai Yue , Andrew Chen
发明人： Bomy Chen , Kai Yue , Andrew Chen
IPC分类号： G11C11/56 , G11C17/00 , G11C17/12 , H01L21/8236 , H01L21/8246 , H01L27/112 , H01L29/76 , H01L29/94 , H01L31/113
CPC分类号： H01L27/11266 , G11C11/5671 , G11C11/5692 , G11C17/123 , H01L27/112
摘要： A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.
摘要翻译：多位只读存储器（ROM）单元具有第一导电类型的具有第一浓度的半导体衬底。彼此间隔开的第二导电类型的第一和第二区域在衬底中。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。门间隔开并与通道的至少第二部分绝缘。 ROM单元具有多个N个可能状态中的一个，其中N大于2. ROM单元的可能状态由存在或不存在在通道的第一部分中形成的延伸或光晕而相邻到与第二区域相邻的第一区域和/或在该通道的第三部分中。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。

66. 发明授权

US07800159B2 Array of contactless non-volatile memory cells 有权
标题翻译：非接触非易失性存储单元阵列
公开(公告)号：US07800159B2
公开(公告)日：2010-09-21
申请号：US11923515
申请日：2007-10-24
申请人： Yuniarto Widjaja , Henry A. O'M'Mani , Prateep Tuntasood , Bomy Chen
发明人： Yuniarto Widjaja , Henry A. O'M'Mani , Prateep Tuntasood , Bomy Chen
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.
摘要翻译：多个非易失性存储单元单元以第一导电类型的单晶半导体衬底中的行和列布置。每个单元单元具有沿着平面的基板中的第二导电类型的第一区域和与第一区域间隔开的第二导电体的第二区域，其间具有沟道区域。通道区域具有与第一区域相邻的第一部分，与第二区域相邻的第三部分和在其间的第二部分。第一和第二浮动栅极分别在第一部分和第三部分之上，并与之绝缘。第一和第二控制栅极分别在第一和第二浮置栅极之上并与其电容耦合。第一和第二擦除栅极分别在第一和第二区域之上并与之绝缘。字线在第二部分之上并与之绝缘。阵列的电触点沿着阵列的末端进行。

67. 发明授权

US07547603B2 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
标题翻译：具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
公开(公告)号：US07547603B2
公开(公告)日：2009-06-16
申请号：US11520993
申请日：2006-09-14
申请人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
摘要翻译：存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

68. 发明授权

US07470949B1 Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing 有权
标题翻译：在沟槽中具有电荷捕获层的这种双向非易失性存储单元和这种存储单元阵列，以及制造方法
公开(公告)号：US07470949B1
公开(公告)日：2008-12-30
申请号：US11828213
申请日：2007-07-25
申请人： Bomy Chen , Yuniarto Widjaja , Jack Edward Frayer , Felix (Ying-Kit) Tsui
发明人： Bomy Chen , Yuniarto Widjaja , Jack Edward Frayer , Felix (Ying-Kit) Tsui
IPC分类号： H01L27/108
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.
摘要翻译：非易失性存储单元具有用于在其上存储电荷的电荷捕获层。电池是第一导电性衬底中的双向电池。电池具有两个间隔开的沟槽。在每个沟槽内，其底部是第二导电性的区域。一个通道从一个沟槽底部的一个区域沿着该沟槽的侧壁延伸到衬底的顶部平坦表面，并且沿相邻沟槽的侧壁延伸到相邻沟槽底部的区域。捕获层沿着两个沟槽中的每一个的侧壁。控制栅极位于每个沟槽中，每个沟槽沿着侧壁电容耦合到捕获层，并且在沟槽的底部与区域电容耦合。每个沟槽可以存储多个位。

69. 发明申请

US20070257299A1 NOR Flash Memory and Fabrication Process 有权
标题翻译： NOR闪存和制造工艺
公开(公告)号：US20070257299A1
公开(公告)日：2007-11-08
申请号：US11381948
申请日：2006-05-05
申请人： Bomy Chen , Prateep Tuntasood , Der-Tsyr Fan
发明人： Bomy Chen , Prateep Tuntasood , Der-Tsyr Fan
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/0425 , G11C16/0433 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42328
摘要： Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates. In another embodiment, the conductors adjacent to the bit line diffusions are program lines, and the third conductors are word lines which extend in a direction perpendicular to the program lines and the diffusions.
摘要翻译：半导体存储器阵列及其制造方法，其中在衬底中形成多个位线扩散，以及在位线扩散之间成对形成的存储单元，其中每对单元具有与位线相邻的第一和第二导体在第一和第二导体旁边的扩散，浮置栅极，浮置栅极之间的擦除栅极以及在擦除栅极下方的衬底中的源极线扩散以及电容耦合到浮动栅极的至少一个附加导体。在一些公开的实施例中，与位线扩散相邻的导体是字线，并且附加导体由耦合到相应浮动栅极的一对耦合栅极或耦合到两个浮动门。在另一个实施例中，与位线扩散相邻的导体是编程线，并且第三导体是在垂直于编程线和扩散的方向上延伸的字线。

70. 发明授权

US07238959B2 Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same 有权
公开(公告)号：US07238959B2
公开(公告)日：2007-07-03
申请号：US10979411
申请日：2004-11-01
申请人： Bomy Chen
发明人： Bomy Chen
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2463 , H01L45/1226 , H01L45/1253 , H01L45/1293 , H01L45/144 , H01L45/16 , Y10S438/90
摘要： A phase change memory device, and method of making the same, that includes a trench formed in insulation material having opposing sidewalls that are inwardly sloping with trench depth. A first electrode is formed in the trench. Phase change memory material is formed in electrical contact with the first electrode. A second electrode is formed in electrical contact with the phase change memory material. Voids are formed in the insulation material to impede heat from the phase change memory material from conducting away therefrom. The voids are formed in pairs, with either a portion of the phase change memory material or the second electrode disposed between the voids.

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