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61. 发明申请

US20090034324A1 NONVOLATILE MEMORY DEVICES THAT INCLUDE A WRITE CIRCUIT THAT WRITES DATA OVER MULTIPLE WRITE PERIODS USING PULSES WHOSE PEAKS DO NOT COINCIDE WITH EACH OTHER 有权
标题翻译：非易失性存储器件，其中包括写入数据的多个写入周期的写入电路，使用峰值不与任何其他值相加的脉冲
公开(公告)号：US20090034324A1
公开(公告)日：2009-02-05
申请号：US12179321
申请日：2008-07-24
申请人： Young-Ran Kim , Ki-Won Lim , Byung-Gil Choi , Ki-Sung Kim
发明人： Young-Ran Kim , Ki-Won Lim , Byung-Gil Choi , Ki-Sung Kim
IPC分类号： G11C7/00 , G11C11/21
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2211/5622
摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cells and a write circuit that is operable to write data to the nonvolatile memory cells over a plurality of consecutive division write periods by generating a plurality of write pulses whose peaks do not coincide with one another to the nonvolatile memory cells.
摘要翻译：非易失性存储器件包括多个非易失性存储器单元和写入电路，该写入电路可操作以通过产生多个写入脉冲将数据写入多个连续的分割写入周期，所述写入脉冲的峰值彼此不一致非易失性存储单元。

62. 发明申请

US20080106922A1 SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF WORD LINE CONTACTS 审中-公开
标题翻译：半导体存储器件和字线接线的布局结构
公开(公告)号：US20080106922A1
公开(公告)日：2008-05-08
申请号：US11735635
申请日：2007-04-16
申请人： Joon-Min Park , Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho
发明人： Joon-Min Park , Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C5/06 , G11C11/00
CPC分类号： G11C11/16 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/76
摘要： A semiconductor memory device and a layout structure of word line contacts, in which the semiconductor memory device includes an active region, a plurality of memory cells, and word line contacts. The active region is disposed in a first direction as a length direction on a semiconductor substrate and is used as a word line. The plurality of memory cells are disposed in the first direction on the active region and are each constructed of one variable resistance device and one diode device. In the word line contacts, at least one each is disposed between respective units, wherein each unit is constructed of predetermined numbers of memory cells on the active region. A bridge effect, such as a short-circuit between adjacent word lines, can be prevented or substantially reduced.
摘要翻译：半导体存储器件和字线触点的布局结构，其中半导体存储器件包括有源区，多个存储单元和字线触点。有源区域沿着半导体衬底上的长度方向的第一方向设置，并用作字线。多个存储单元在有源区域上沿第一方向设置，并且分别由一个可变电阻器件和一个二极管器件构成。在字线触点中，每个单元之间至少设置一个，其中每个单元由有源区上的预定数量的存储单元构成。可以防止或显着减少诸如相邻字线之间的短路的桥接效应。

63. 发明授权

US07075848B2 Redundancy circuit in semiconductor memory device having a multiblock structure 有权
标题翻译：具有多块结构的半导体存储器件中的冗余电路
公开(公告)号：US07075848B2
公开(公告)日：2006-07-11
申请号：US10889194
申请日：2004-07-12
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C17/18
CPC分类号： G11C29/812 , G11C29/806
摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
摘要翻译：一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

64. 发明申请

US20050195633A1 Method for programming phase-change memory array to set state and circuit of a phase-change memory device 有权
标题翻译：用于编程相变存储器阵列以设置相变存储器件的状态和电路的方法
公开(公告)号：US20050195633A1
公开(公告)日：2005-09-08
申请号：US11070196
申请日：2005-03-03
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
IPC分类号： G11C13/02 , G11C13/00 , G11C16/02 , G11C16/10 , G11C19/08 , H01L27/10 , H01L27/105 , H01L27/115
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.
摘要翻译：一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

65. 发明授权

US08254159B2 Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation 有权
标题翻译：对执行读写操作的非易失性半导体存储器件的位线进行放电的方法
公开(公告)号：US08254159B2
公开(公告)日：2012-08-28
申请号：US12662512
申请日：2010-04-21
申请人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
发明人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/72 , G11C2213/79
摘要： In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.
摘要翻译：在执行读写操作的非易失性半导体存储器件的放电位线的方法中。该方法包括在第一周期内基于写入命令将全局写入位线放电到接地电压。该方法还包括在第二周期期间将全局写入位线的放电电压保持在接地电压中。

66. 发明授权

US08098518B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08098518B2
公开(公告)日：2012-01-17
申请号：US12476875
申请日：2009-06-02
申请人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
发明人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
摘要翻译：非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位开关。列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。

67. 发明申请

US20110026306A1 RESISTANCE VARIABLE MEMORY DEVICE REDUCING WORD LINE VOLTAGE 有权
标题翻译：电阻可变存储器件减少字线电压
公开(公告)号：US20110026306A1
公开(公告)日：2011-02-03
申请号：US12903279
申请日：2010-10-13
申请人： Byung-Gil Choi , Du-Eung KIM
发明人： Byung-Gil Choi , Du-Eung KIM
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.
摘要翻译：电阻可变存储器件包括存储单元阵列，读出放大器电路和列选择电路。存储单元阵列包括多个块单元和多个字线驱动器，其中每个块单元连接在相邻字线驱动器之间并且包括多个存储块。读出放大器电路包括多个读出放大器单元，其中每个读出放大器单元向对应的块单元提供读取电流并且包括多个读出放大器。列选择电路连接在存储单元阵列和读出放大器电路之间，并响应于列选择信号选择多个存储块中的至少一个，以将读出的电流从读出放大器电路施加到所选存储块。

68. 发明授权

US07835199B2 Nonvolatile memory using resistance material 有权
标题翻译：使用电阻材料的非易失性存储器
公开(公告)号：US07835199B2
公开(公告)日：2010-11-16
申请号：US12244042
申请日：2008-10-02
申请人： Joon-Yong Choi , Byung-Gil Choi , Du-Eung Kim
发明人： Joon-Yong Choi , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C7/20 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C2207/2227 , G11C2213/72 , G11C2213/79
摘要： Provided is a nonvolatile memory using a resistance material. In embodiments of the invention, a PRAM is configured to apply a step-down voltage to wordlines during a standby mode. Aspects of the present invention thus provide a nonvolatile memory with reduced standby current. Additionally, embodiments of the invention allow for faster transition from a standby state to an active state.
摘要翻译：提供了使用电阻材料的非易失性存储器。在本发明的实施例中，PRAM被配置为在待机模式期间对字线施加降压电压。因此，本发明的方面提供了具有减少的待机电流的非易失性存储器。另外，本发明的实施例允许从待机状态到活动状态的更快的转换。

69. 发明授权

US07808817B2 Nonvolatile memory device using resistive elements and an associated driving method 有权
标题翻译：使用电阻元件的非易失性存储器件和相关的驱动方法
公开(公告)号：US07808817B2
公开(公告)日：2010-10-05
申请号：US12186649
申请日：2008-08-06
申请人： Beak-Hyung Cho , Byung-Gil Choi
发明人： Beak-Hyung Cho , Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A nonvolatile memory device is configured to increase the reliability of a write operation by providing a sufficiently high write current while reducing current consumption in a read operation. The nonvolatile memory device includes a memory cell array having a plurality of nonvolatile memory cells. A global bit line and a local bit line coupled to a plurality of the nonvolatile memory cells. The local bit line has first and second nodes. First and second bit line selection circuits are included where the first bit line selection circuit is coupled to the first node of the local bit line and the second bit line selection circuit is coupled to the second node of the local bit line. The first and second bit line selection circuits operate during a first period to electrically connect the local bit line to the global bit line, and only one of the first and second bit line selection circuits operates during a second period to electrically connect the local bit line to the global bit line.
摘要翻译：非易失性存储器件被配置为通过提供足够高的写入电流来提高写入操作的可靠性，同时减少读取操作中的电流消耗。非易失性存储器件包括具有多个非易失性存储单元的存储单元阵列。耦合到多个非易失性存储器单元的全局位线和局部位线。本地位线具有第一和第二节点。包括第一位线选择电路和第二位线选择电路，其中第一位线选择电路耦合到本地位线的第一节点，而第二位线选择电路耦合到本地位线的第二节点。第一位线选择电路和第二位线选择电路在第一周期期间操作以将局部位线电连接到全局位线，并且在第二周期期间仅第一位线选择电路和第二位线选择电路中只有一个电连接局部位线到全局位线。

70. 发明申请

US20100067279A1 SEMICONDUCTOR MEMORY DEVICE USING VARIABLE RESISTOR 有权
标题翻译：使用可变电阻器的半导体存储器件
公开(公告)号：US20100067279A1
公开(公告)日：2010-03-18
申请号：US12622536
申请日：2009-11-20
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00 , G11C5/02
CPC分类号： G11C8/14 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028
摘要： Example embodiments relate to a variable resistance semiconductor memory device including: a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other; and a line selecting unit simultaneously selecting word lines of the plurality of memory blocks and simultaneously selecting bit lines of the memory blocks belonging to the same memory sector among the plurality of memory blocks in an access operation mode.
摘要翻译：示例实施例涉及一种可变电阻半导体存储器件，包括：属于不同存储器扇区的多个存储块，并且交替地布置在包括存储器扇区的存储体中以彼此相邻; 以及线选择单元，同时选择多个存储块的字线，并且在访问操作模式中同时选择属于同一存储器扇区的存储器块的位线。

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