专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07221036B1 BJT with ESD self protection 有权
标题翻译： BJT具有ESD自保护功能
公开(公告)号：US07221036B1
公开(公告)日：2007-05-22
申请号：US11129957
申请日：2005-05-16
申请人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0821
摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
摘要翻译：将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。

62. 发明授权

US07119431B1 Apparatus and method for forming heat sinks on silicon on insulator wafers 有权
标题翻译：用于在绝缘体硅片上形成散热片的装置和方法
公开(公告)号：US07119431B1
公开(公告)日：2006-10-10
申请号：US10665897
申请日：2003-09-18
申请人： Peter J. Hopper , Iouri Mirgorodski , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Iouri Mirgorodski , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L23/34 , H01L27/12
CPC分类号： H01L29/78606 , H01L23/3677 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.
摘要翻译：散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。该装置包括形成在晶片的有源硅层中的晶体管。活性表面形成在氧化物层和体硅层上。在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。塞子延伸穿过本体层的厚度到氧化物层。此后，塞子填充有导热材料，例如金属或DAG（导热浆）。在运行期间，来自晶体管的热量通过散热器消散。在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。

63. 发明授权

US06911679B1 LVTSCR with compact design 有权
标题翻译： LVTSCR设计紧凑
公开(公告)号：US06911679B1
公开(公告)日：2005-06-28
申请号：US10339202
申请日：2003-01-09
申请人： Vladislav Vashchenko , Ann Concannon , Marcel ter Beek , Peter J. Hopper
发明人： Vladislav Vashchenko , Ann Concannon , Marcel ter Beek , Peter J. Hopper
IPC分类号： H01L27/02 , H01L29/417
CPC分类号： H01L27/0262
摘要： In an ESD protection device making use of a LVTSCR, at least one contacted drain and at least one emitter are formed, and are arranged laterally next to each other to be substantially equidistant from the gate of the LVTSCR, to improve holding voltage and decrease size. The ratio of emitter width to contacted drain width is adjusted to achieve the desired characteristics.
摘要翻译：在使用LVTSCR的ESD保护装置中，形成至少一个接触漏极和至少一个发射极，并且彼此横向地布置成与LVTSCR的栅极基本等距，以提高保持电压并减小尺寸。调节发射极宽度与接触漏极宽度的比率以达到所需的特性。

64. 发明授权

US06667867B2 Stable BJT electrostatic discharge protection clamp 有权
公开(公告)号：US06667867B2
公开(公告)日：2003-12-23
申请号：US09767934
申请日：2001-01-23
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H02H900
CPC分类号： H02H9/046
摘要： In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a BJT acting as an avalanche diode is reduced by injecting current into the base of the BJT. This is achieved through the use of a capacitor connected between Vdd and the base of the avalanche BJT to speed up the switching of the protection circuit.

65. 发明授权

US06560081B1 Electrostatic discharge (ESD) protection circuit 有权
标题翻译：静电放电（ESD）保护电路
公开(公告)号：US06560081B1
公开(公告)日：2003-05-06
申请号：US09690558
申请日：2000-10-17
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H02H900
CPC分类号： H02H9/046 , H01L27/0259 , H01L2924/0002 , H02H3/006 , H01L2924/00
摘要： An ESD protection circuit that can be easily configured to provide ESD event protection against a range of ESD event voltages. The circuit is also compatible with high frequency ICs. The ESD protection circuit includes an input terminal configured to receive an ESD event signal and a diode sub-circuit. The diode sub-circuit includes at least one diode (e.g., either a single diode or a plurality of diodes connected in series or parallel configuration), a diode input node and a diode output node. The diode sub-circuit is configured to receive an ESD event signal from the input terminal and to operate under forward bias conditions to provide a diode output signal at the diode output node. The circuit also includes a bipolar junction transistor (e.g., a Si—Ge bipolar junction transistor) with a base, a collector and an emitter. The emitter is configured to receive the ESD event signal from the input terminal, while the base is configured to receive the diode output signal from the diode output node. A resistor, with a resistor input node, a resistor output node and an output terminal, is also included in the circuit. The resistor input node is electrically connected to the diode output node and the output terminal is connected to the resistor output node, the emitter and ground. By predetermining the electrical characteristics (e.g., forward bias voltage) and number of diodes in the diode sub-circuit, the circuit can be adapted to provide ESD protection against a range of ESD event voltages.
摘要翻译： ESD保护电路可以轻松配置，以提供ESD事件保护，防止一系列ESD事件电压。该电路还兼容高频IC。 ESD保护电路包括被配置为接收ESD事件信号的输入端子和二极管子电路。二极管子电路包括至少一个二极管（例如，串联或并联配置连接的单个二极管或多个二极管），二极管输入节点和二极管输出节点。二极管子电路被配置为从输入端子接收ESD事件信号并且在正向偏置条件下操作以在二极管输出节点处提供二极管输出信号。该电路还包括具有基极，集电极和发射极的双极结型晶体管（例如，Si-Ge双极结型晶体管）。发射极被配置为从输入端子接收ESD事件信号，而基极配置为从二极管输出节点接收二极管输出信号。电路中还包括一个带有电阻输入节点的电阻，一个电阻输出节点和一个输出端子。电阻输入节点电连接到二极管输出节点，输出端子连接到电阻输出节点，发射极和地。通过预先确定二极管子电路中的电特性（例如，正向偏置电压）和二极管的数量，该电路可适用于针对一系列ESD事件电压提供ESD保护。

66. 发明授权

US06541801B1 Triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes 有权
标题翻译：具有大于待受保护节点上的直流偏置电压的保持电压的三端双向可控硅开关
公开(公告)号：US06541801B1
公开(公告)日：2003-04-01
申请号：US09782389
申请日：2001-02-12
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L2974
CPC分类号： H01L27/0262 , H01L29/87
摘要： The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.
摘要翻译：三端双向可控硅开关元件的保持电压（操作所需的最小电压）增加到大于被保护节点上的直流偏置的值。通过在每个p +区域和被保护节点之间插入电压降来增加保持电压。因此，三端双向可控硅开关可用于为电源引脚提供ESD保护。

67. 发明申请

US20120273881A1 DMOS Transistor with a Cavity that Lies Below the Drift Region 有权
标题翻译：具有位于漂移区下方的腔的DMOS晶体管
公开(公告)号：US20120273881A1
公开(公告)日：2012-11-01
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

68. 发明申请

US20120261753A1 DMOS Transistor with a Slanted Super Junction Drift Structure 有权
标题翻译：具有倾斜超结结漂移结构的DMOS晶体管
公开(公告)号：US20120261753A1
公开(公告)日：2012-10-18
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

69. 发明申请

US20120154956A1 Self protected snapback device driven by driver circuitry using high side pull-up avalanche diode 审中-公开
标题翻译：使用高侧上拉雪崩二极管的驱动电路驱动的自保护快速恢复装置
公开(公告)号：US20120154956A1
公开(公告)日：2012-06-21
申请号：US12928714
申请日：2010-12-17
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H02H7/00
CPC分类号： H01L27/0255 , H01L27/0285 , H01L29/7817 , H01L29/7821 , H02H9/046 , H03K17/0822 , H03K17/122
摘要： In a power device such as an NLDMOS power array comprising multiple NLDMOS devices, the gates of which are driven by a driver, self protection against overvoltage events is implemented by providing a high side pull-up avalanche diode connected to at least some of the gates of the NLDMOS devices.
摘要翻译：在诸如包括多个NLDMOS器件的NLDMOS功率阵列的功率器件中，其门由驱动器驱动，通过提供连接到至少一些栅极的高侧上拉雪崩二极管实现过压事件的自我保护的NLDMOS设备。

70. 发明授权

US07754540B2 Method of forming a SiGe DIAC ESD protection structure 有权
标题翻译：形成SiGe DIAC ESD保护结构的方法
公开(公告)号：US07754540B2
公开(公告)日：2010-07-13
申请号：US12395506
申请日：2009-02-27
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L21/332
CPC分类号： H01L27/0259
摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.
摘要翻译：用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式