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1. 发明授权

US08878295B2 DMOS transistor with a slanted super junction drift structure 有权
标题翻译：具有倾斜超结漂移结构的DMOS晶体管
公开(公告)号：US08878295B2
公开(公告)日：2014-11-04
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

2. 发明申请

US20120273881A1 DMOS Transistor with a Cavity that Lies Below the Drift Region 有权
标题翻译：具有位于漂移区下方的腔的DMOS晶体管
公开(公告)号：US20120273881A1
公开(公告)日：2012-11-01
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

3. 发明申请

US20120261753A1 DMOS Transistor with a Slanted Super Junction Drift Structure 有权
标题翻译：具有倾斜超结结漂移结构的DMOS晶体管
公开(公告)号：US20120261753A1
公开(公告)日：2012-10-18
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

4. 发明授权

US08524548B2 DMOS Transistor with a cavity that lies below the drift region 有权
标题翻译：具有位于漂移区下方的空腔的DMOS晶体管
公开(公告)号：US08524548B2
公开(公告)日：2013-09-03
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/66
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

5. 发明授权

US07714355B1 Method of controlling the breakdown voltage of BSCRs and BJT clamps 有权
标题翻译：控制BSCR和BJT夹具击穿电压的方法
公开(公告)号：US07714355B1
公开(公告)日：2010-05-11
申请号：US11312704
申请日：2005-12-20
申请人： Vladislav Vashchenko , Alexei Sadovnikov , Peter J. Hopper , Andy Strachan
发明人： Vladislav Vashchenko , Alexei Sadovnikov , Peter J. Hopper , Andy Strachan
IPC分类号： H01L29/74
CPC分类号： H01L29/7322 , H01L29/0821 , H01L29/74
摘要： In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
摘要翻译：在BSCR或BJT ESD钳位中，通过屏蔽收集器的一部分来控制BJT器件的集电极的尺寸来控制击穿电压和直流电压公差。

6. 发明授权

US06964907B1 Method of etching a lateral trench under an extrinsic base and improved bipolar transistor 有权
标题翻译：在外部基极和改进的双极晶体管之下蚀刻横向沟槽的方法
公开(公告)号：US06964907B1
公开(公告)日：2005-11-15
申请号：US10716276
申请日：2003-11-17
申请人： Peter J. Hopper , Alexei Sadovnikov , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Alexei Sadovnikov , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L21/302 , H01L21/306 , H01L21/331 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/732
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
摘要翻译：在BJT中，通过在外部基极区域和集电极之间形成横向沟槽来减小外部基极到集电极电容。这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。

7. 发明授权

US08648391B2 SiGe heterojunction bipolar transistor with an improved breakdown voltage-cutoff frequency product 有权
标题翻译： SiGe异质结双极晶体管具有改进的击穿电压截止频率积
公开(公告)号：US08648391B2
公开(公告)日：2014-02-11
申请号：US13429262
申请日：2012-03-23
申请人： Jeffrey A. Babcock , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Alexei Sadovnikov
IPC分类号： H01L29/66
CPC分类号： H01L29/66242 , H01L21/76232 , H01L21/76283 , H01L27/0825 , H01L27/0826 , H01L29/0646 , H01L29/0649 , H01L29/0821 , H01L29/7371
摘要： The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
摘要翻译： SiGe异质结双极晶体管（HBT）的击穿电压（BVCEO）和截止频率（fT）的乘积通过利用具有从基极向下延伸的中空芯的掺杂区域而增加到约翰逊极限以上，掺杂的埋地集电区。掺杂区域和掩埋集电极区域具有相反的掺杂剂类型。

8. 发明授权

US06528862B1 Bipolar transistor with a box-type germanium profile that lies outside of the emitter-base depletion region 有权
标题翻译：位于发射极 - 基极耗尽区之外的具有盒型锗分布的双极晶体管
公开(公告)号：US06528862B1
公开(公告)日：2003-03-04
申请号：US10125897
申请日：2002-04-19
申请人： Alexei Sadovnikov
发明人： Alexei Sadovnikov
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The upper epitaxial layer of a bipolar transistor has a silicon germanium layer and an overlying cap layer. The upper epitaxial layer includes an intrinsic emitter region and a base region. The silicon germanium layer is spaced apart from the intrinsic emitter region, and lies outside of the depletion region associated with the junction between the intrinsic emitter region and the base region.
摘要翻译：双极晶体管的上部外延层具有硅锗层和上覆盖层。上部外延层包括本征发射极区域和基极区域。硅锗层与本征发射极区域间隔开，并且位于与本征发射极区域和基极区域之间的结点相关联的耗尽区域的外部。

9. 发明授权

US08207559B2 Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures 有权
标题翻译：肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法
公开(公告)号：US08207559B2
公开(公告)日：2012-06-26
申请号：US12498141
申请日：2009-07-06
申请人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov , Zia Alan Shafi
发明人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov , Zia Alan Shafi
IPC分类号： H01L29/66
CPC分类号： H01L27/095 , H01L27/0207 , H01L29/1029 , H01L29/1058 , H01L29/808 , H01L29/812
摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.
摘要翻译：根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接场效应晶体管（JFET）。在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。

10. 发明申请

US20110065256A1 SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES 审中-公开
标题翻译：用于增加LOCOS隔离装置的突然电压的系统和方法
公开(公告)号：US20110065256A1
公开(公告)日：2011-03-17
申请号：US12955194
申请日：2010-11-29
申请人： Richard W. Foote, JR. , Terry Lee Lines , Alexei Sadovnikov , Andy Strachan
发明人： Richard W. Foote, JR. , Terry Lee Lines , Alexei Sadovnikov , Andy Strachan
IPC分类号： H01L21/762
CPC分类号： H01L21/76205
摘要： An efficient method is disclosed for increasing the breakdown voltage of an integrated circuit device that is isolated by a local oxidation of silicon (LOCOS) process. The method comprises forming a portion of a field oxide in an integrated circuit so that the field oxide has a gradual profile. The gradual profile of the field oxide reduces impact ionization in the field oxide by creating a reduced value of electric field for a given value of applied voltage. The reduction in impact ionization increases the breakdown voltage of the integrated circuit. The gradual profile is formed by using an increased thickness of pad oxide and a reduced thickness of silicon nitride during a field oxide oxidation process.
摘要翻译：公开了一种有效的方法来增加由硅（LOCOS）工艺的局部氧化隔离的集成电路器件的击穿电压。该方法包括在集成电路中形成场氧化物的一部分，使得场氧化物具有逐渐的轮廓。场氧化物的逐渐轮廓通过为给定的施加电压值产生减小的电场值来减少场氧化物中的冲击电离。冲击电离的减少增加了集成电路的击穿电压。通过在场氧化物氧化过程中通过使用增加的衬垫氧化物的厚度和减小的氮化硅的厚度来形成渐变曲线。

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