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61. 发明申请

US20080258181A1 Hybrid Substrates and Methods for Forming Such Hybrid Substrates 失效
标题翻译：混合底物和形成这种杂交基质的方法
公开(公告)号：US20080258181A1
公开(公告)日：2008-10-23
申请号：US11737989
申请日：2007-04-20
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Jack Allan Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/76243 , H01L21/76251 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
摘要翻译：以不同晶体取向的半导体岛为特征的混合基板和形成这种混合基板的方法。该方法涉及使用SIMOX工艺来形成绝缘层。绝缘层可以将不同晶体取向中的至少一个的岛分成相互排列的器件和体区。身体区域可以相对于装置区域电浮动。

62. 发明授权

US06583462B1 Vertical DRAM having metallic node conductor 有权
标题翻译：具有金属节点导体的垂直DRAM
公开(公告)号：US06583462B1
公开(公告)日：2003-06-24
申请号：US09702338
申请日：2000-10-31
申请人： Toshiharu Furukawa , Rajarao Jammy , Thomas Kanarsky , Jeffrey John Welser , David Vaclav Horak , Steven John Holmes , Mark Charles Hakey
发明人： Toshiharu Furukawa , Rajarao Jammy , Thomas Kanarsky , Jeffrey John Welser , David Vaclav Horak , Steven John Holmes , Mark Charles Hakey
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867
摘要： A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.
摘要翻译：形成在具有沟槽的衬底中的动态随机存取存储器件。沟槽具有侧壁，顶部，下部和圆周。该装置包括信号存储节点，该信号存储节点包括形成在沟槽下部的金属存储节点导体，并通过节点电介质和节点电介质上方的环形氧化物与侧壁隔离。优选地，沟槽具有大于50的纵横比。掩埋带耦合到存储节点导体并且接触环形氧化物上方的沟槽的侧壁的一部分。形成在掩埋带上的沟槽电介质具有沟槽顶部的电介质厚度。信号传送装置包括：第一扩散区域，其延伸到与所述掩埋带接触的所述沟槽侧壁的所述部分相邻的所述衬底;门绝缘体，其具有形成在所述第一掩埋带的上方的所述沟槽侧壁上的栅绝缘体厚度，绝缘体厚度小于沟槽顶部电介质厚度，以及形成在沟槽顶部电介质并且邻近栅极绝缘体的沟槽内的栅极导体。

63. 发明授权

US6063658A Methods of making a trench storage DRAM cell including a step transfer device 失效
标题翻译：制造包括步进转移装置的沟槽存储DRAM单元的方法
公开(公告)号：US6063658A
公开(公告)日：2000-05-16
申请号：US172865
申请日：1998-10-15
申请人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
发明人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.
摘要翻译：存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域，至少一个FET并且具有比所述至少一个FET更大的深度。所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。

64. 发明申请

US20080261363A1 DUAL GATED FINFET GAIN CELL 有权
标题翻译：双栅金刚石增益电池
公开(公告)号：US20080261363A1
公开(公告)日：2008-10-23
申请号：US12144139
申请日：2008-06-23
申请人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Mark Eliot Masters , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Mark Eliot Masters , Peter H. Mitchell
IPC分类号： H01L21/8242
CPC分类号： H01L27/108 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.
摘要翻译：用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。第一栅电极与存储装置电耦合。第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。当门控时，电流的大小取决于存储设备存储的电量。

65. 发明申请

US20080206937A1 WRAP-AROUND GATE FIELD EFFECT TRANSISTOR 失效
标题翻译：封边栅场效应晶体管
公开(公告)号：US20080206937A1
公开(公告)日：2008-08-28
申请号：US12114180
申请日：2008-05-02
申请人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Peter H. Mitchell
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/78645 , H01L29/78648
摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.
摘要翻译：形成具有环绕，垂直排列的双栅电极的场效应晶体管。从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。第二次回蚀将栅极导体材料的一部分移除第二距离。第一和第二距离之间的差异定义了最终设备的栅极长度。剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

66. 发明授权

US07791145B2 Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures 有权
标题翻译：用于闭锁抑制的半导体结构和形成这种半导体结构的方法
公开(公告)号：US07791145B2
公开(公告)日：2010-09-07
申请号：US11764571
申请日：2007-06-18
申请人： Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L27/092
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

67. 发明授权

US07655985B2 Methods and semiconductor structures for latch-up suppression using a conductive region 失效
公开(公告)号：US07655985B2
公开(公告)日：2010-02-02
申请号：US12125381
申请日：2008-05-22
申请人： Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823878 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

68. 发明授权

US07727848B2 Methods and semiconductor structures for latch-up suppression using a conductive region 失效
标题翻译：使用导电区域进行闩锁抑制的方法和半导体结构
公开(公告)号：US07727848B2
公开(公告)日：2010-06-01
申请号：US12169806
申请日：2008-07-09
申请人： Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/331
CPC分类号： H01L27/0921 , H01L21/823878 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

69. 发明授权

US07397692B1 High performance single event upset hardened SRAM cell 有权
标题翻译：高性能单事件硬化SRAM单元
公开(公告)号：US07397692B1
公开(公告)日：2008-07-08
申请号：US11612809
申请日：2006-12-19
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack A. Mandelman
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.
摘要翻译：一个SRAM单元。 SRAM单元包括第一CMOS反相器和第二CMOS反相器，连接到第二反相器的输出的第一反相器的输入和连接到第一反相器的输出的第二反相器的输入，第一CMOS反相器的输出和第一电容器的第一板，第一电容器的第二板连接到电源的高电压端子; 插入在所述第二CMOS反相器的输出端和第二电容器的第一板之间的第二MOSFET，所述第二电容器的第二板连接到所述电源的高电压端子; 以及连接到第一MOSFET的栅极和第二MOSFET的栅极的控制信号线。

70. 发明授权

US07517716B2 Method of forming optical sensor that includes three pairs of electrodes formed at different depths in a semiconductor substrate 失效
标题翻译：一种形成光学传感器的方法，包括在半导体衬底中形成在不同深度的三对电极
公开(公告)号：US07517716B2
公开(公告)日：2009-04-14
申请号：US12042375
申请日：2008-03-05
申请人： Toshiharu Furukawa , Steven J. Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Steven J. Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： H01L31/18
CPC分类号： H01L31/101 , H01L27/14647 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for forming an optical sensor. First, a structure which comprises a semiconductor substrate is provided. Then, a first electrode and a fourth electrode are formed at a first depth in the semiconductor substrate. Then, a second electrode and a fifth electrode are formed at a second depth in the semiconductor substrate. Then, a third electrode and a sixth electrode are formed at a third depth in the semiconductor substrate. The first depth is greater than the second depth which is greater than the third depth. First, second, and third semiconducting regions of the semiconductor substrate are disposed between and in direct physical contact with the first and fourth electrodes, the second and fifth electrodes, and the third and sixth electrodes, respectively. The first, second, and third semi-conducting regions are in direct physical contact with one another.
摘要翻译：一种形成光学传感器的方法。首先，提供包括半导体衬底的结构。然后，第一电极和第四电极形成在半导体衬底中的第一深度处。然后，在半导体衬底中以第二深度形成第二电极和第五电极。然后，第三电极和第六电极形成在半导体衬底中的第三深度处。第一深度大于大于第三深度的第二深度。半导体衬底的第一，第二和第三半导体区域分别设置在第一和第四电极，第二和第五电极以及第三和第六电极之间并与之直接物理接触。第一，第二和第三半导体区域彼此直接物理接触。

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