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61. 发明授权

US06509763B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06509763B2
公开(公告)日：2003-01-21
申请号：US10162565
申请日：2002-06-06
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G01R1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

62. 发明授权

US06272069B1 LSI device with memory and logics mounted thereon 有权
公开(公告)号：US06272069B1
公开(公告)日：2001-08-07
申请号：US09764446
申请日：2001-01-19
申请人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
发明人： Hiroyoshi Tomita , Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C800
摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

63. 发明授权

US06239631B1 Integrated circuit device with input buffer capable of correspondence with highspeed clock 有权
标题翻译：具有与高速时钟对应的输入缓冲器的集成电路器件
公开(公告)号：US06239631B1
公开(公告)日：2001-05-29
申请号：US09377104
申请日：1999-08-19
申请人： Shinya Fujioka , Hiroyoshi Tomita
发明人： Shinya Fujioka , Hiroyoshi Tomita
IPC分类号： H03L700
CPC分类号： G11C7/1093 , G06F5/06 , G11C7/1087 , G11C7/222 , H03L7/00
摘要： One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable receive of input signals.
摘要翻译：本发明的一个方面的特征在于，输入缓冲电路构成2组或相对于1个输入信号的多组，一对互补的内部时钟或多个内部时钟通过分频产生集成电路器件内的提供的时钟和输入信号可以与一对互补时钟同步地接收和锁存，或者根据两组或多组的输入缓冲器与多个时钟同步地被接收和锁存。 2组或多组的输入缓冲器的输出由组合电路组合，并在内部提供。为内部产生的内部时钟设置一个H电平或一个L电平周期，使得各种输入缓冲器的输出不会相互竞争。根据本发明，多个组的输入缓冲器的操作与比所提供的时钟慢的内部时钟同步，因此能够可靠地接收输入信号。

64. 发明授权

US06198689B1 Integrated circuit device with built-in self timing control circuit 有权
标题翻译：具有内置自定时控制电路的集成电路器件
公开(公告)号：US06198689B1
公开(公告)日：2001-03-06
申请号：US09440667
申请日：1999-11-16
申请人： Masafumi Yamazaki , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Masafumi Yamazaki , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： The present invention is an integrated circuit device having a self timing control circuit for generating an input loading timing signal whose phase is adjusted with an external clock, where loading of input signals supplied from outside, such as a command input signal, address input signal and data input signal, to internal circuits is forbidden when the self timing control circuit is adjusting phase. And when the self timing control circuit finishes adjusting the phase to a certain degree, the loading operation of an input signal at the input circuit using the input loading timing signal is enabled. To execute such an operation, the input circuit generates an input loading control signal based on a lock-on signal or adjustment signal of the DLL circuit, or based on an input stop cancellation signal, for example. The input circuit controls the stop and restart of loading of the input signal according to this input loading control signal.
摘要翻译：本发明是一种具有自定时控制电路的集成电路装置，该自定时控制电路用于产生输入负载定时信号，该输入负载定时信号的相位是用外部时钟调整的，其中从外部输入的输入信号如命令输入信号，地址输入信号和数据输入信号，当自定时控制电路正在调整相位时，禁止内部电路。并且当自定时控制电路在一定程度上完成相位调整时，可以使用输入负载定时信号在输入电路处的输入信号的加载操作。为了执行这种操作，输入电路基于例如DLL电路的锁定信号或调整信号，或者基于输入停止消除信号，生成输入负载控制信号。输入电路根据该输入负载控制信号控制输入信号的停止和重新启动。

65. 发明授权

US06194932B1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US06194932B1
公开(公告)日：2001-02-27
申请号：US09383015
申请日：1999-08-25
申请人： Yoshihiro Takemae , Yasurou Matsuzaki , Hiroyoshi Tomita , Nobutaka Taniguchi
发明人： Yoshihiro Takemae , Yasurou Matsuzaki , Hiroyoshi Tomita , Nobutaka Taniguchi
IPC分类号： H03L700
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03L7/0814
摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.
摘要翻译：本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定时信号相匹配。然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。

66. 发明授权

US06181184B2 Variable delay circuit and semiconductor intergrated circuit device 失效
标题翻译：可变延迟电路和半导体集成电路器件
公开(公告)号：US06181184B2
公开(公告)日：2001-01-30
申请号：US09089397
申请日：1998-06-03
申请人： Masafumi Yamazaki , Hiroyoshi Tomita
发明人： Masafumi Yamazaki , Hiroyoshi Tomita
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K5/131 , H03K2005/00058 , H03L7/0805 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.
摘要翻译：可变延迟电路包括信号传输线上的负载，连接到信号传输线的至少一个晶体管。每个晶体管由其栅极电压控制，使得信号传输线上的信号响应于与其连接的栅极电容的大小而被延迟。

67. 发明授权

US06181174B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06181174B2
公开(公告)日：2001-01-30
申请号：US09404221
申请日：1999-09-23
申请人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814
摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
摘要翻译：半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。延迟系统包括延迟虚拟时钟的可变延迟电路。控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。

68. 发明授权

US6144595A Semiconductor device performing test operation under proper conditions 有权
标题翻译：在适当条件下进行测试操作的半导体器件
公开(公告)号：US6144595A
公开(公告)日：2000-11-07
申请号：US131880
申请日：1998-08-10
申请人： Osamu Hirooka , Hiroyoshi Tomita , Tatsuya Kanda
发明人： Osamu Hirooka , Hiroyoshi Tomita , Tatsuya Kanda
IPC分类号： G01R31/28 , G11C11/401 , G11C11/407 , G11C29/02 , G11C29/12 , G11C29/34 , G11C7/00
CPC分类号： G11C29/12 , G11C29/02
摘要： A semiconductor device outputs data from a plurality of data nodes during a normal-operation mode, and outputs a test result from at least one of the data nodes during a test-operation mode. The semiconductor device includes a plurality of data-bus lines which convey the data with respect to the data nodes, and a data-bus switch which allows only the data-bus lines corresponding to the at least one of the data nodes to be driven in a first condition of the test-operation mode, and which allows all of the data-bus lines corresponding to the data nodes to be driven in a second condition of the test-operation mode.
摘要翻译：半导体器件在正常操作模式期间从多个数据节点输出数据，并且在测试操作模式期间从至少一个数据节点输出测试结果。半导体器件包括相对于数据节点传送数据的多条数据总线，以及数据总线开关，该数据总线开关只允许与至少一个数据节点相对应的数据总线线驱动测试操作模式的第一条件，并且允许在测试操作模式的第二条件下驱动对应于数据节点的所有数据总线。

69. 发明授权

US6108793A Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device 失效
标题翻译：具有时序稳定电路的半导体器件和测试这种半导体器件的方法
公开(公告)号：US6108793A
公开(公告)日：2000-08-22
申请号：US40288
申请日：1998-03-18
申请人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
发明人： Yasuhiro Fujii , Hiroyoshi Tomita , Nobutaka Taniguchi , Yasurou Matsuzaki
IPC分类号： G01R31/30 , G06F1/04 , H03L7/081 , H03L7/087 , H03L7/095
CPC分类号： H03L7/0805 , G01R31/3016 , G06F1/04 , H03L7/0814 , H03L7/087 , H03L7/095
摘要： A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.
摘要翻译：一种测量定时稳定电路所需的时间的方法，以便对具有第一功能的半导体器件完成定时稳定以复位定时稳定电路，以及第二功能，以输出指示完成的信号公开了定时稳定。该方法包括以下步骤：a）激活定时稳定电路，b）通过使用第二功能来检测定时稳定的定时，以及c）测量定时稳定电路完成定时所需的时间基于时间稳定。

70. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

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