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61. 发明授权

US5983314A Output buffer having inherently precise data masking 失效
标题翻译：具有固有精确数据掩蔽的输出缓冲器
公开(公告)号：US5983314A
公开(公告)日：1999-11-09
申请号：US898177
申请日：1997-07-22
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/10 , G06F13/00 , G06F3/00
CPC分类号： G11C7/1006 , G11C7/1009 , G11C7/1051 , G11C7/1057
摘要： A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.
摘要翻译：可屏蔽数据输出缓冲器包括从数据编码器接收数据信号的输出级。从数据编码器输出的信号通常是对应于互补数据输入信号的互补数据信号。然而，响应于接收到掩码信号，数据编码器迫使输出信号不是互补的。输出级通常产生对应于互补数据输入信号的数据输出信号。然而，当数据输入信号不是互补时，输出级的输出呈现高阻抗状态。由于高阻抗条件的定时是从数据信号本身确定的，所以掩蔽操作的定时固有地适当地定时到来自数据输出缓冲器的数据的输出。

62. 再颁专利

USRE36264E Read circuit for accessing dynamic random access memories (DRAMs) 失效
标题翻译：用于访问动态随机存取存储器（DRAM）的读电路
公开(公告)号：USRE36264E
公开(公告)日：1999-08-03
申请号：US684338
申请日：1996-07-19
申请人： Todd A. Merritt , Greg A. Blodgett
发明人： Todd A. Merritt , Greg A. Blodgett
IPC分类号： G11C7/10 , G11C11/4093 , G11C11/4096 , H03K19/00 , H03K17/08
CPC分类号： G11C7/1057 , G11C11/4093 , G11C11/4096 , G11C7/1051 , G11C7/106 , H03K19/0013
摘要： DRAM read accessing circuitry having two parallel connected control lines, one of which includes a level translator stage and the other of which includes an enable gate. Both the level translator stage and the enable gate are connected to receive 0.0 to 3 volt small logic swings from output buffer logic utilized in reading data out of the DRAM. Output signals from the level translator stage are applied to a pull up output transistor in an output driver stage, and output signals from the enable gate are connected to a pull down output transistor in the output driver stage. A feedback connection is provided between the output of the level translator stage and one input to the enable gate to ensure that the enable gate does not generate an enabling output signal for turning on the pull down output transistor until the pull up output transistor is completely turned off. Not only does this novel operation completely eliminate crossing or crossover currents in the output driver stage, but it also introduces minimum time delays in logic swings at the output node of the output driver stage.
摘要翻译： DRAM读取存取电路具有两个并联的控制线，其中一个包括电平转换器级，另一个包括一个使能门。电平转换器级和使能栅都被连接以从用于从DRAM读出数据中使用的输出缓冲器逻辑接收0.0至3伏小的逻辑摆幅。来自电平转换器级的输出信号被施加到输出驱动级中的上拉输出晶体管，并且来自使能栅极的输出信号连接到输出驱动级中的下拉输出晶体管。在电平转换器级的输出和允许栅极的一个输入之间提供反馈连接，以确保使能栅极不产生用于导通下拉输出晶体管的使能输出信号，直到上拉输出晶体管完全转向关闭这种新颖的操作不仅完全消除了输出驱动级中的交叉或交叉电流，而且还在输出驱动级的输出节点的逻辑摆幅中引入了最小的时间延迟。

63. 发明授权

US5895962A Structure and a method for storing information in a semiconductor device 失效
标题翻译：用于在半导体器件中存储信息的结构和方法
公开(公告)号：US5895962A
公开(公告)日：1999-04-20
申请号：US664109
申请日：1996-06-13
申请人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
发明人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
IPC分类号： G01R31/3181 , G11C17/10 , H01L27/112 , H01L27/04 , G11C17/00
CPC分类号： G01R31/3181 , G11C17/10 , H01L27/112
摘要： A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer. Each of the storage elements is formed in a predetermined state such that they collectively store a digital value that identifies a mask used to form the conductive layer.
摘要翻译：半导体器件包括形成在衬底上的多个导电层。共同组成存储元件的只读存储元件（例如熔丝元件）的两个电互相耦合部分分别形成在不同的一个导电层中。存储元件具有存储状态，并且每个部分具有导电性。可以通过改变其中一个部分的电导率来改变存储元件的存储状态。另外，多个存储元件可以并联耦合以形成存储模块。存储模块的每个存储元件可以包括各自形成在不同导电层中的多个存储部分。存储元件可以存储用于形成半导体器件的掩模集的版本号。或者，在衬底上形成导电层，并且在导电层中形成一个或多个只读存储元件。每个存储元件形成为预定状态，使得它们共同地存储识别用于形成导电层的掩模的数字值。

64. 发明授权

US5877987A Method and circuit for self-latching data read lines in the data output path of a semiconductor memory device 失效
标题翻译：用于在半导体存储器件的数据输出路径中自锁锁数据读取线的方法和电路
公开(公告)号：US5877987A
公开(公告)日：1999-03-02
申请号：US799357
申请日：1997-02-14
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/10 , G11C29/12 , G11C29/48 , G11C16/04
CPC分类号： G11C7/106 , G11C29/12 , G11C29/48 , G11C7/1006 , G11C7/103 , G11C7/1051
摘要： A method and circuit for self-latching data read lines that are used to transfer data that is read from a memory array of a memory device to a data output register of the memory device, wherein a self-latching latch circuit is connected to each data read line. The latch circuits are located physically near the output of the memory array, for latching data that is read from the memory array as soon as the data is applied to the data read lines, and prior to the data being latched in the data output register, thereby minimizing the effects of propagation delay so that the memory cycle time can be decreased. In one embodiment wherein the memory is organized in a "x4" configuration, different groups of the data read lines are selected in alternate read cycles, and the data read lines of the non-selected data read group are equilibrated automatically during the read cycle using the conventional test circuits of the memory device.
摘要翻译：一种用于自锁存数据读取线的方法和电路，用于将从存储器件的存储器阵列读取的数据传送到存储器件的数据输出寄存器，其中自锁存锁存电路连接到每个数据读行。锁存电路位于物理靠近存储器阵列的输出处，用于锁存从存储器阵列读取的数据，一旦数据被施加到数据读取线，并且在数据被锁存在数据输出寄存器中之前，从而最小化传播延迟的影响，从而可以减少存储周期时间。在其中存储器被组织成“x4”配置的一个实施例中，在备用读取周期中选择不同组的数据读取行，并且在读取循环期间自动平衡未选择的数据读取组的数据读取行存储器件的常规测试电路。

65. 发明授权

US5812462A Integrated circuit clock input buffer 失效
公开(公告)号：US5812462A
公开(公告)日：1998-09-22
申请号：US832437
申请日：1997-04-03
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/10 , G11C7/22 , H03K5/151 , G11C7/00
CPC分类号： G11C7/225 , G11C7/1072 , G11C7/22 , H03K5/151
摘要： An integrated circuit clock buffer is described which includes output circuits for generating internal clock signals in response to an externally provided clock signal. The clock buffer includes a latch circuit having a delayed feedback to provide a pulsed signal in response to a transition in the external clock signal. The output circuits have a trip point which is skewed in one direction to detect a rising transition of the pulsed signal, and are skewed in a second direction to detect a falling transition of the pulsed signal. The buffer generates two non-skewed internal clock signals which have sharp rising and falling transitions.

66. 发明授权

US5781486A Apparatus for testing redundant elements in a packaged semiconductor memory device 失效
公开(公告)号：US5781486A
公开(公告)日：1998-07-14
申请号：US633133
申请日：1996-04-16
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/00 , G11C29/24
CPC分类号： G11C29/24
摘要： During compression mode testing of a semiconductor memory device, a memory address is compressed to free up 2 or more bits in the address (e.g., an 11-bit address is compressed to 9-bits, freeing up 2 bits). Redundant element enable circuitry is coupled to one or more pins on a packaged chip that are unused during the compression mode testing. The circuitry receives control signals from external testing circuitry to select between the primary memory array in the chip, and redundant rows and columns of memory in the chip. As a result, during compressed address mode testing of the chip, a full 11-bit word is input to test the circuitry, but where 2 of the 11 bits allow the external circuitry to toggle between, and thereby selectively access, the rows and columns of primary and redundant memory in the chip. Alternatively, the circuitry can also be coupled to a non-connected pin on the packaged chip so as to operate during a non-compression mode testing.

67. 发明授权

US08743628B2 Line driver circuits, methods, and apparatuses 有权
标题翻译：线路驱动器电路，方法和装置
公开(公告)号：US08743628B2
公开(公告)日：2014-06-03
申请号：US13204994
申请日：2011-08-08
申请人： Tae H. Kim , Howard C. Kirsch , Yu-Wen Huang , Mingshiang Wang , Todd A. Merritt
发明人： Tae H. Kim , Howard C. Kirsch , Yu-Wen Huang , Mingshiang Wang , Todd A. Merritt
IPC分类号： G11C7/00
CPC分类号： G11C11/4085 , G11C7/18 , G11C8/08
摘要： Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.
摘要翻译：描述的实施例涉及线路驱动器，例如用于在存储器阵列中提供减小的栅极感应漏极泄漏的线路驱动器。还公开了线路驱动器的相应的操作方法。

68. 发明申请

US20110093662A1 MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY 有权
标题翻译：具有内部处理器的内存和内存中的数据通信方法
公开(公告)号：US20110093662A1
公开(公告)日：2011-04-21
申请号：US12603376
申请日：2009-10-21
申请人： Robert M. Walker , Dan Skinner , Todd A. Merritt , J. Thomas Pawlowski
发明人： Robert M. Walker , Dan Skinner , Todd A. Merritt , J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/067 , G06F3/0683 , G06F9/3001 , G06F9/30043 , G06F12/0813 , G06F13/4068 , G06F15/7821
摘要： Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).
摘要翻译：提供具有内部处理器的存储器，以及在这种存储器内的数据通信方法。在一个实施例中，内部处理器可以经由一个或多个缓冲器同时访问存储器设备上的存储器阵列上的一个或多个存储体。内部处理器可以耦合到能够访问多于一个存储体的缓冲器，或者耦合到多个缓冲器，每个缓冲器可以访问存储体，从而可以同时从不同的存储体中检索数据并存储在其中。此外，存储器设备可以被配置为通过存储器组件（诸如耦合到每个内部处理器的缓冲器）之间的耦合来在一个或多个内部处理器之间进行通信。因此，可以由不同的内部处理器执行多操作指令，并且可以将来自一个内部处理器的数据（例如中间结果）传送到存储器的另一内部处理器，从而能够并行执行指令。

69. 发明授权

US07218561B2 Apparatus and method for semiconductor device repair with reduced number of programmable elements 有权
标题翻译：具有减少可编程元件数量的半导体器件修复的装置和方法
公开(公告)号：US07218561B2
公开(公告)日：2007-05-15
申请号：US11293946
申请日：2005-12-05
申请人： Timothy B. Cowles , Todd A. Merritt
发明人： Timothy B. Cowles , Todd A. Merritt
IPC分类号： G11C7/00
CPC分类号： G11C29/812 , G11C29/787 , G11C2029/4402
摘要： An apparatus and method using a reduced number of nonvolatile programming elements for enabling redundant memory blocks in a semiconductor memory is disclosed. A redundancy selection module may be configured using N fuses to configure and select 2N-1 repair modules. Programming fuses effectively separates the repair modules into two sets, those with an even address and those with an odd address. Each repair module contains fuses programmed with a selected address, such that the repair module may respond when an address input matches the selected address. However, the least significant bit is left out of the programming. As a result, repair modules in the even set respond to even addresses matching the selected address and repair modules in the odd set respond to odd addresses matching the selected address. Similar arrangements may be used to reduce the number of enable fuses and disable fuses required for each repair module.
摘要翻译：公开了一种使用减少数量的非易失性编程元件来实现半导体存储器中的冗余存储块的装置和方法。可以使用N个熔丝来配置冗余选择模块来配置和选择2个N 1修复模块。编程保险丝将修复模块有效地分为两组，即具有偶数地址和奇数地址的组。每个维修模块都包含用选定地址编程的保险丝，使得当地址输入与选定地址匹配时，修复模块可以响应。然而，最低有效位不在编程之中。因此，偶数集中的修复模块响应偶数地址匹配所选择的地址和奇数组中的修复模块对与所选地址匹配的奇数地址进行响应。可以使用类似的布置来减少启用保险丝的数量并禁用每个维修模块所需的保险丝。

70. 发明授权

US07137050B2 Compression circuit for testing a memory device 失效
标题翻译：用于测试存储器件的压缩电路
公开(公告)号：US07137050B2
公开(公告)日：2006-11-14
申请号：US10712150
申请日：2003-11-13
申请人： Todd A. Merritt , Nicholas VanHeel
发明人： Todd A. Merritt , Nicholas VanHeel
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/40
摘要： An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.
摘要翻译：一种用于测试具有多条数据线的存储器件的装置，包括输入电路，压缩电路和输出电路。输入电路适于接收数据线的至少第一子集和多个使能信号。每个使能信号与数据线的第一子集中的至少一个相关联。压缩电路耦合到输入电路，并适于检测数据线的第一子集上的预定图案。当在数据线的第一子集上检测到预定模式时，输出电路耦合到压缩电路并适于提供至少一个通过信号。输入电路能够基于相关联的使能信号来屏蔽来自压缩电路的数据线的第一子集中的至少一个。

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