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    • 65. 发明授权
    • Method of forming high-luminescence silicon electroluminescence device
    • 形成高发光硅电致发光器件的方法
    • US07259055B2
    • 2007-08-21
    • US11066713
    • 2005-02-24
    • Tingkai LiPooran Chandra JoshiWei GaoYoshi OnoSheng Teng Hsu
    • Tingkai LiPooran Chandra JoshiWei GaoYoshi OnoSheng Teng Hsu
    • H01L21/8238
    • H01L31/03046Y02E10/544Y02P70/521
    • A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).
    • 提供一种用于形成高发光Si电致发光(EL)荧光体的方法,其具有由Si荧光体制成的EL器件。 该方法包括:用Si纳米晶体沉积富含氧的氧化物(SRO)膜,折射率在1.5至2.1范围内,孔隙率在5至20%的范围内; 并且在氧气氛中对SRO膜进行后退火。 DC溅射或PECVD工艺可用于沉积SRO膜。 在一个方面,该方法还包括:HF缓冲氧化物蚀刻(BOE)SRO膜; 并且再次氧化SRO膜,以在SRO膜中的Si纳米晶体周围形成SiO 2层。 在一个方面,SRO膜通过在氧气气氛中退火再次氧化。 以这种方式,在具有1至5纳米(nm)范围内的厚度的Si纳米晶体周围形成SiO 2层。
    • 68. 发明授权
    • Asymmetric memory cell
    • 不对称记忆单元
    • US06927074B2
    • 2005-08-09
    • US10442627
    • 2003-05-21
    • Sheng Teng HsuTingkai LiDavid R. Evans
    • Sheng Teng HsuTingkai LiDavid R. Evans
    • H01L27/10G11C11/15G11C13/00H01L21/8246H01L27/105H01L43/08H01L21/00
    • G11C13/0007B82Y10/00G11C11/15G11C2213/31G11C2213/52H01L45/04H01L45/1233H01L45/1253H01L45/147
    • An asymmetric memory cell and method for forming an asymmetric memory cell are provided. The method comprises: forming a bottom electrode having a first area; forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode; forming a top electrode overlying the EPVR layer having a second area, less than the first area. In some aspects the second area is at least 20% smaller than the first area. The EPVR is a material such as colossal magnetoresistance (CMR), high temperature super conducting (HTSC), or perovskite metal oxide materials. The method further comprises: inducing an electric field between the electrodes; inducing current flow through the EPVR adjacent the top electrode; and, in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR. Typically, the resistance is modified within the range of 100 ohms to 10 mega-ohms.
    • 提供了一种用于形成非对称存储单元的非对称存储单元和方法。 该方法包括:形成具有第一区域的底部电极; 形成覆盖底部电极的各种电阻(EPVR)材料的电脉冲; 形成覆盖在EPVR层上的顶部电极,其具有小于第一区域的第二区域。 在一些方面,第二区域比第一区域小至少20%。 EPVR是诸如巨磁阻(CMR),高温超导(HTSC)或钙钛矿金属氧化物材料的材料。 该方法还包括:在电极之间引入电场; 通过邻近顶部电极的EPVR引起电流流动; 并且响应于通过与顶部电极相邻的EPVR的电流流动,修改EPVR的电阻。 通常,电阻在100欧姆到10兆欧姆的范围内被修改。
    • 70. 发明授权
    • Ferroelectric nonvolatile transistor and method of making same
    • 铁电非易失性晶体管及其制造方法
    • US6048740A
    • 2000-04-11
    • US187238
    • 1998-11-05
    • Sheng Teng HsuJer-shen MaaFengyang ZhangTingkai Li
    • Sheng Teng HsuJer-shen MaaFengyang ZhangTingkai Li
    • H01L21/8247H01L21/336H01L21/8246H01L27/10H01L27/105H01L29/78H01L29/788H01L29/792H01L29/76
    • H01L29/6684H01L29/78391
    • A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.
    • 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口,以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠,其中所述FE栅极堆叠具有L2的宽度,其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。 铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域,源极区域和漏极区域,沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构,所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠,其中所述FE栅极堆叠具有L2的宽度,其中L2> / = L1 +2δ,其中Δ是光刻工艺的对准公差。