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61. 发明授权

US5847462A Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 失效
标题翻译：集成电路具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US5847462A
公开(公告)日：1998-12-08
申请号：US748812
申请日：1996-11-14
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： An interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

62. 发明授权

US5827776A Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines 失效
标题翻译：制造集成电路的方法，其使用蚀刻停止件来产生交错的互连线
公开(公告)号：US5827776A
公开(公告)日：1998-10-27
申请号：US959106
申请日：1997-10-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/768 , H01L21/76816 , H01L23/5226 , H01L2924/0002
摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.
摘要翻译：提供了多层互连结构。多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。三个导体中的两个导体在单独的垂直和水平平面中彼此交错。第三导体有利地在两个第二导体的至少一部分之间隔开横向距离。第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

63. 发明授权

US5783481A Semiconductor interlevel dielectric having a polymide for producing air gaps 失效
标题翻译：具有用于产生气隙的聚酰亚胺的半导体层间电介质
公开(公告)号：US5783481A
公开(公告)日：1998-07-21
申请号：US659167
申请日：1996-06-05
申请人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L2924/0002
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors. A combination of polyimide, air gaps (air-filled cavities) and deposited dielectric forms an inter-level dielectric structure having a low dielectric permittivity or dielectric constant in critical conductor spaces.
摘要翻译：提供介电材料，其具有在水平或垂直间隔的导体之间的介电沉积期间形成的气隙。电介质沉积在聚酰亚胺上，其中聚酰亚胺被放置在下面的导体层之上和之间。当覆盖的电介质沉积在聚酰亚胺上时，聚酰亚胺材料脱气形成聚酰亚胺和电介质之间的空气分离。空气分离在紧密间隔的导体之间的区域和每个导体正上方的高高度区域中是特别普遍的。介电沉积工艺优选包括两个沉积循环。使用第一沉积温度来强制显着的除气，并且需要第二沉积循环来封闭可能存在于紧密间隔的导体之间的任何和所有键孔。聚酰亚胺，气隙（充气腔）和沉积的电介质的组合形成在临界导体空间中具有低介电常数或介电常数的层间电介质结构。

64. 发明授权

US06208015B1 Interlevel dielectric with air gaps to lessen capacitive coupling 失效
标题翻译：具有气隙的间隔电介质以减少电容耦合
公开(公告)号：US06208015B1
公开(公告)日：2001-03-27
申请号：US09014192
申请日：1998-01-27
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L2358
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.
摘要翻译：布置在两层互连之间的半导体器件中的介电常数介电层的介电常数降低。电介质包括第一电介质层，优选地来自沉积在第一级互连上的硅烷源，以在相邻的第一互连结构之间的中点处形成气隙;第二电介质，其以间隔开的间隔跨越第二电介质包含气隙沟槽，以及形成的第三电介质在所述第二电介质上。在第三电介质上形成第二互连电平。

65. 发明授权

US6127264A Integrated circuit having conductors of enhanced cross-sectional area 有权
标题翻译：集成电路具有增强的横截面积的导体
公开(公告)号：US6127264A
公开(公告)日：2000-10-03
申请号：US166463
申请日：1998-10-05
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L23/522 , H01L23/528 , H01L21/4763 , H01L21/44 , H01L23/48
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

66. 发明授权

US6054356A Transistor and process of making a transistor having an improved LDD masking material 失效
标题翻译：晶体管和制造具有改进的LDD掩模材料的晶体管的工艺
公开(公告)号：US6054356A
公开(公告)日：2000-04-25
申请号：US761332
申请日：1996-12-10
申请人： Robert Dawson , Mark W. Michael , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , Fred N. Hause
IPC分类号： H01L21/266 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/6659 , H01L29/7833
摘要： A transistor is provided with a gradually increasing source and drain arsenic doping profile in a lateral direction from the gate conductor sidewall surfaces. The very smooth doping profile ensures small electric fields at the channel-drain interface for the benefit of reducing hot-carrier effects. Such a doping profile may be achieved by performing the ion implantation through a non-conformal layer of spin-on glass. By controlling the viscosity of the SOG and its deposition speed, different meniscus shapes may be formed. The doping profile of the arsenic in the source and drain regions follows the profile of the upper surface of the SOG. Arsenic is advantageously used for both the lightly doped and heavily doped regions of the source/drain junctions. Arsenic has lower mobility compared to phosphorus and is better at maintaining its original doping profile in heating of the device during further processing. Too much alteration in the original doping profile over time may change the device characteristics beyond acceptable levels.
摘要翻译：晶体管在栅极导体侧壁表面的横向上设置有逐渐增加的源极和漏极砷掺杂分布。非常平滑的掺杂分布确保了通道 - 漏极界面的小电场，有利于减少热载流子效应。这种掺杂分布可以通过通过旋涂玻璃的非保形层进行离子注入来实现。通过控制SOG的粘度及其沉积速度，可以形成不同的弯液面形状。源极和漏极区域中的砷的掺杂分布遵循SOG的上表面的轮廓。砷有利地用于源极/漏极结的轻掺杂区域和重掺杂区域。砷与磷相比具有较低的迁移率，并且在进一步加工期间更好地保持其在加热装置中的原始掺杂特性。随着时间的推移，原始掺杂特性的变化可能会将器件特性改变为可接受的水平。

67. 发明授权

US5899727A Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 失效
标题翻译：制造由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区域的方法
公开(公告)号：US5899727A
公开(公告)日：1999-05-04
申请号：US642155
申请日：1996-05-02
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76205 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
摘要翻译：提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。隔离过程导致在紧邻有源区域的场区域中形成沟槽。然而，这个沟槽并不完全穿过田野区域。通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

68. 发明授权

US5830773A Method for forming semiconductor field region dielectrics having globally planarized upper surfaces 失效
标题翻译：用于形成具有全局平坦化的上表面的半导体场区电介质的方法
公开(公告)号：US5830773A
公开(公告)日：1998-11-03
申请号：US634757
申请日：1996-04-17
申请人： William S. Brennan , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Mark W. Michael
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/768 , H01L21/31
CPC分类号： H01L21/76819 , H01L21/31055 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.
摘要翻译：提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。隔离过程导致间隔开的多个场电介质，其具有彼此基本上共面的上表面和相邻的硅台面上表面。因此，隔离过程是与浅沟槽技术一起使用的平坦化工艺，其中将蚀刻增强离子转移到该电介质的上部高度区域的填充电介质中。当经受随后的蚀刻剂时，掺杂剂导致以比较低的高度区域更快的速率除去较高的高度区域。因此，掺杂剂的选择性放置和蚀刻去除预先将填充电介质上表面全局地横跨整个晶片进行预处理。在主要在较高高度区域蚀刻去除之后，将剩余的填充电介质上表面去除到与硅台面的上表面相当的水平，由此产生介于硅台面之间的单独的场电介质。场电介质，无论它们的横向面积如何，每个在相邻的硅台面处或稍低于相邻的硅台面处都具有基本平坦的上表面。通过产生平面场电介质上表面，从形成在场电介质上或场电介质和硅台面之间的薄膜中去除了各种非平面性问题。

69. 发明授权

US5792706A Interlevel dielectric with air gaps to reduce permitivity 失效
标题翻译：具有气隙的层间电介质以降低介电常数
公开(公告)号：US5792706A
公开(公告)日：1998-08-11
申请号：US658457
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： A reduced permittivity interlevel dielectric is provided. The interlevel dielectric is formed between two levels of interconnect. The interlevel dielectric comprises a first dielectric layer formed from a TEOS source deposited on a first level interconnect. The first dielectric contains air gaps at spaced intervals across the first dielectric. A second dielectric, preferably from a silane source is deposited upon said first dielectric. A second interconnect level is then placed on the second dielectric.
摘要翻译：提供了一种降低介电常数的层间电介质。层间电介质形成在两层互连之间。层间电介质包括由沉积在第一层互连上的TEOS源形成的第一介质层。第一电介质以间隔开的间隔跨越第一电介质。第二电介质，优选由硅烷源沉积在所述第一电介质上。然后将第二互连电平放置在第二电介质上。

70. 发明授权

US5767012A Method of forming a recessed interconnect structure 失效
标题翻译：形成凹陷互连结构的方法
公开(公告)号：US5767012A
公开(公告)日：1998-06-16
申请号：US660674
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , H01L21/283
CPC分类号： H01L23/5222 , H01L21/768 , H01L2924/0002
摘要： A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.
摘要翻译：提供一种形成凹陷互连结构的方法。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。形成凹陷互连结构的方法包括在半导体衬底上形成基本共面的第一导体组，在第一导体上沉积第一电介质层，在第一电介质层中形成沟槽，在沟槽中沉积导电材料，对导电材料进行平面化，导电材料的上表面与第一电介质的上表面基本共面，蚀刻导电材料，直到导电材料的上表面位于第一电介质的上表面以下，形成第二电介质在导电材料和第一介电层上。

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