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61. 发明申请

US20090106584A1 STORAGE APPARATUS AND METHOD FOR CONTROLLING THE SAME 有权
标题翻译：存储装置及其控制方法
公开(公告)号：US20090106584A1
公开(公告)日：2009-04-23
申请号：US12024206
申请日：2008-02-01
申请人： Yosuke NAKAYAMA , Hiromi Matsushige , Hiroshi Suzuki
发明人： Yosuke NAKAYAMA , Hiromi Matsushige , Hiroshi Suzuki
IPC分类号： G06F11/08
CPC分类号： G06F11/1088 , G06F11/0727 , G06F11/0748 , G06F11/076 , G06F11/0793 , G06F2211/109
摘要： Provided is a storage apparatus that can dramatically shorten the time for recovery from a fault in a storage device. In a storage apparatus provided with one or more storage devices and a method for controlling the storage apparatus, when a fault occurs in the storage device, whether or not the fault is a predetermined specific fault is judged, and the storage device is rebooted if the fault is the predetermined specific fault. As a result, recovery from the fault can be achieved in a dramatically shorter amount of time than the time required for replacement of the storage device. Accordingly, the time for recovery from the fault in the storage device can be shortened dramatically.
摘要翻译：提供了可以显着缩短从存储设备中的故障恢复的时间的存储装置。在设置有一个以上的存储装置的存储装置和控制存储装置的方法中，当存储装置发生故障时，判断故障是否是预定的特定故障，并且如果存储装置重启故障是预定的特定故障。因此，可以以比更换存储设备所需的时间更短的时间量来实现故障恢复。因此，可以显着缩短从存储装置的故障中恢复的时间。

62. 发明授权

US08250453B2 Storage apparatus and data verification method in storage apparatus 有权
标题翻译：存储装置中的存储装置和数据验证方法
公开(公告)号：US08250453B2
公开(公告)日：2012-08-21
申请号：US12309138
申请日：2008-12-22
申请人： Hiromi Matsushige
发明人： Hiromi Matsushige
IPC分类号： G06F7/02
CPC分类号： G06F11/0727 , G06F11/0757
摘要： When a data write request to a disk drive 210 is received from a host computer 20, a first error detecting code of write data to be written to the disk drive 210 in response to the data write request is generated and stored, write processing of the write data to the disk drive 210 is executed, whether or not response time as time required for the write processing exceeds a predetermined threshold value is determined, data stored in a sector as a writing destination of the write data is read from the sector when the response time exceeds the threshold value, a second error detecting code of the read data is generated, and when the first error detecting code and the second error detecting code are compared with each other and the two codes do not coincide with each other, a signal indicating that the write processing is not normally performed is generated.
摘要翻译：当从主计算机20接收到对磁盘驱动器210的数据写入请求时，产生并存储要响应于数据写入请求写入到磁盘驱动器210的写数据的第一错误检测码，执行向磁盘驱动器210的写入数据，确定写入处理所需的响应时间是否超过预定阈值，作为写入数据的写入目的地的扇区中存储的数据从扇区读取时响应时间超过阈值，生成读取数据的第二错误检测码，并且当第一错误检测码和第二错误检测码相互比较且两个码不相符时，信号指示不正常执行写入处理。

63. 发明授权

US4695909A Magnetic head assembly 失效
标题翻译：磁头组件
公开(公告)号：US4695909A
公开(公告)日：1987-09-22
申请号：US669583
申请日：1984-11-08
申请人： Kazuhiro Momata , Yoshinori Dekura , Tadashi Honzawa , Hiromi Matsushige
发明人： Kazuhiro Momata , Yoshinori Dekura , Tadashi Honzawa , Hiromi Matsushige
IPC分类号： G11B5/29 , G11B5/10 , G11B5/127 , G11B5/187 , G11B15/64
CPC分类号： G11B15/64 , G11B5/10
摘要： A magnetic head for recording and reproducing information on and from a flexible magnetic recording tape. The active face of tape supporting protrusions formed in the magnetic head is so configured that the contacting area between the supporting protrusion and the recording tape is smaller at both end portions of the protrusion than an intermediate portion thereof as viewed in the direction widthwise of the recording tape, whereby improved contacting state and floating state between the magnetic head and the recording tape can be assured over the whole width of the flexible recording tape.
摘要翻译：用于在柔性磁记录带上记录和再现信息的磁头。形成在磁头中的带支撑突起的主动面被构造成使得突出部的两个端部处的支撑突起和记录带之间的接触面积比其记录方向的宽度方向上的中间部分小磁带，从而可以在柔性记录带的整个宽度上确保磁头和记录带之间的改善的接触状态和浮动状态。

64. 发明申请

US20110185268A1 Storage apparatus and data verification methd in storage apparatus 有权
标题翻译：存储装置中的存储装置和数据验证方法
公开(公告)号：US20110185268A1
公开(公告)日：2011-07-28
申请号：US12309138
申请日：2008-12-22
申请人： Hiromi Matsushige
发明人： Hiromi Matsushige
IPC分类号： H03M13/09 , G06F11/07
CPC分类号： G06F11/0727 , G06F11/0757
摘要： When a data write request to a disk drive 210 is received from a host computer 20, a first error detecting code of write data to be written to the disk drive 210 in response to the data write request is generated and stored, write processing of the write data to the disk drive 210 is executed, whether or not response time as time required for the write processing exceeds a predetermined threshold value is determined, data stored in a sector as a writing destination of the write data is read from the sector when the response time exceeds the threshold value, a second error detecting code of the read data is generated, and when the first error detecting code and the second error detecting code are compared with each other and the two codes do not coincide with each other, a signal indicating that the write processing is not normally performed is generated.
摘要翻译：当从主计算机20接收到对磁盘驱动器210的数据写入请求时，产生并存储要响应于数据写入请求写入到磁盘驱动器210的写数据的第一错误检测码，执行向磁盘驱动器210的写入数据，确定作为写入处理所需的时间的响应时间是否超过预定阈值，当存储在作为写入数据的写入目的地的扇区中存储的数据从扇区读取时响应时间超过阈值，生成读取数据的第二错误检测码，并且当第一错误检测码和第二错误检测码相互比较且两个码不相符时，信号指示不正常执行写入处理。

65. 发明授权

US5414571A Adaptive equalization circuit for magnetic recording apparatus having high error immunity 失效
标题翻译：用于具有高误码抗扰度的磁记录装置的自适应均衡电路
公开(公告)号：US5414571A
公开(公告)日：1995-05-09
申请号：US961623
申请日：1992-10-16
申请人： Hiromi Matsushige , Minoru Kosuge , Yasuhiro Shimura , Hideki Miyasaka , Satoshi Minoshima , Tsuguji Tachiuchi , Kazunori Iwabuchi , Terumi Takashi , Naoto Matsunami
发明人： Hiromi Matsushige , Minoru Kosuge , Yasuhiro Shimura , Hideki Miyasaka , Satoshi Minoshima , Tsuguji Tachiuchi , Kazunori Iwabuchi , Terumi Takashi , Naoto Matsunami
IPC分类号： H03H15/00 , G11B5/035 , G11B20/10 , G11B20/18 , H03H17/00 , H03H21/00 , H03K5/159 , H04B3/04 , H04L25/03 , G11B5/35 , H03H7/30 , H03H7/40
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/10046 , G11B5/035 , H03K5/159 , H04L25/03038
摘要： A data reproducing circuit having a magnetic head for reading data from a recording medium, an adaptive equalization circuit for optimizing the waveform of a read signal, a discriminator circuit for discriminating an output signal of the adaptive equalization circuit and outputting a discriminated signal to an upper stage circuit, a format detecting circuit for detecting a pattern of signals written on the recording medium from outputs of the magnetic head, an expected value generating circuit for generating an expected value of the waveform of the read signal in accordance with an output of the adaptive equalization circuit and an output of the discriminator circuit, and an error detecting circuit for generating an error signal representing a difference between an output of the adaptive equalization circuit and an output of the expected value generating circuit. In the data reproducing circuit, the adaptive equalization characteristic of the adaptive equalization circuit is changed when a particular signal pattern on the recording medium is detected, allowing the adaptive equalization operation suitable for the recording medium.
摘要翻译：一种具有用于从记录介质读取数据的磁头的数据再现电路，用于优化读取信号的波形的自适应均衡电路，用于鉴别自适应均衡电路的输出信号并将鉴别信号输出到上位的鉴频电路格式检测电路，用于根据磁头的输出来检测写在记录介质上的信号的模式;期望值产生电路，用于根据自适应的输出产生读取信号的波形的期望值均衡电路和鉴别器电路的输出;以及误差检测电路，用于产生表示自适应均衡电路的输出与预期值产生电路的输出之间的差的误差信号。在数据再现电路中，当检测到记录介质上的特定信号图案时，自适应均衡电路的自适应均衡特性改变，允许适合于记录介质的自适应均衡操作。

66. 发明授权

US5841303A Digital phase-locked loop circuit 失效
标题翻译：数字锁相环电路
公开(公告)号：US5841303A
公开(公告)日：1998-11-24
申请号：US742678
申请日：1996-10-31
申请人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
发明人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
IPC分类号： H03K5/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/10 , H03L7/085
CPC分类号： H03L7/10 , H03L7/093
摘要： Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
摘要翻译：来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF 5。 LPF5还包括相位补偿器6和周期补偿器，用于通过数字滤波器7中的内部相位误差DELTA N来补偿控制延迟体验。由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1用于确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并存储在其中作为误差数据Ne。因此，采集时间缩短，稳态误差的数量也减少。

67. 发明授权

US5625632A Magnetic disk drive including a data discrimination apparatus capable of correcting signal waveform distortion due to intersymbol interference 失效
标题翻译：磁盘驱动器包括能够校正由于符号间干扰引起的信号波形失真的数据鉴别装置
公开(公告)号：US5625632A
公开(公告)日：1997-04-29
申请号：US319725
申请日：1994-10-07
申请人： Yoshiteru Ishida , Kazunori Iwabuchi , Hideyuki Yamakawa , Hiromi Matsushige
发明人： Yoshiteru Ishida , Kazunori Iwabuchi , Hideyuki Yamakawa , Hiromi Matsushige
IPC分类号： G11B20/10 , G06F11/10 , H03M13/00
CPC分类号： G11B20/10009
摘要： A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols "0" and "1" to obtain a run length of the symbol "0" with respect to a given symbol "1" (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same. The thus corrected equalizer output is data discriminated in a data discrimination circuit, with a lowered error rate owing to the correction.
摘要翻译：一种数据识别装置，其能够校正由校正值识别的要被数据的信号的幅度的降低，以便校正用作目标位的位本身以确定校正值。判定电路预先将均衡器输出分类为符号“0”和“1”，以获得相对于给定符号“1”（目标位）的符号“0”的游程长度。校正值产生电路包括存储器件，其存储与游程长度的所有可能值相对应的校正值，并且响应于来自判定电路的输出将一个校正值输出存储器件。延迟电路使均衡器输出延迟所需的时间，直到校正值被输出。操作电路将所选择的校正值与延迟均衡器输出相加，以校正相同的值。这样校正的均衡器输出是在数据鉴别电路中鉴别的数据，由于校正而导致的误差率降低。

68. 发明授权

US5231544A Method and apparatus for signal detection in a magnetic recording and reproducing apparatus 失效
标题翻译：在磁记录和再现装置中用于信号检测的方法和装置
公开(公告)号：US5231544A
公开(公告)日：1993-07-27
申请号：US646670
申请日：1991-01-28
申请人： Hiromi Matsushige
发明人： Hiromi Matsushige
IPC分类号： G11B20/10 , G11B20/14
CPC分类号： G11B20/10009 , G11B20/1426
摘要： A signal detection circuit of a magnetic recording and reproducing apparatus generates a clock signal synchronized with peaks of a reproduced signal read from a magnetic recording medium on which data have been recorded by a (d, k) run-length code, and determines "1" or "0" with respect to a discrimination threshold based on an absolute value of a peak of the reproduced waveform at a timing synchronized with the clock signal. The signal detection circuit comprises a quantizer for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal, a multi-stage shift register for delaying the clock signal in synchronism with the clock signal, and threshold generation means for comparing the quantized signal supplied from the final stage of the multi-stage shift register and the quantized signal representing the current threshold to dynamically generate a new relevant threshold in accordance with the difference in the comparison.
摘要翻译：磁记录和重放装置的信号检测电路产生与通过（d，k）游程长度码记录有数据的磁记录介质读出的再现信号的峰值同步的时钟信号，并确定“1 基于与时钟信号同步的定时的再生波形的峰值的绝对值，判定阈值为“或”0“。信号检测电路包括量化器，用于与时钟信号同步地量化再现信号以产生量化信号;多级移位寄存器，用于与时钟信号同步地延迟时钟信号;以及阈值产生装置，用于将量化的信号从多级移位寄存器的最后级提供的信号和表示当前阈值的量化信号，以根据比较的差异动态生成新的相关阈值。

69. 发明授权

US5572157A Digital phase-looked loop circuit 失效
标题翻译：数字相位环路电路
公开(公告)号：US5572157A
公开(公告)日：1996-11-05
申请号：US21854
申请日：1993-02-24
申请人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
发明人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
IPC分类号： H03K5/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/10 , H03L7/085
CPC分类号： H03L7/10 , H03L7/093
摘要： Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
摘要翻译：来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF5。 LPF5还包括相位补偿器6和周期补偿器8，用于通过数字滤波器7中的内相位误差DELTA N补偿控制延迟体验。使用由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1 用于确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并作为误差数据Ne存储。因此，采集时间缩短，稳态误差的数量也减少。

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