专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07282402B2 Method of making a dual strained channel semiconductor device 有权
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：US07282402B2
公开(公告)日：2007-10-16
申请号：US11093801
申请日：2005-03-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

62. 发明授权

US07160769B2 Channel orientation to enhance transistor performance 有权
标题翻译：通道方向增强晶体管性能
公开(公告)号：US07160769B2
公开(公告)日：2007-01-09
申请号：US10969108
申请日：2004-10-20
申请人： Ted R. White , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823807 , H01L27/092 , H01L29/045
摘要： P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.
摘要翻译： P沟道晶体管形成在具有用于增强P沟道晶体管性能的（110）表面取向的半导体层中，并且N沟道晶体管形成在具有（100）表面取向的半导体层中。为了进一步提供P沟道晶体管性能增强，它们的沟道长度的方向根据其沟道方向来选择。窄宽度P沟道晶体管优选地在<100>方向上取向。宽通道宽度P沟道晶体管优选地在<110>方向上取向。

63. 发明授权

US07091071B2 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer 有权
标题翻译：半导体制造工艺包括在SOI晶片中的凹陷源极/漏极区域
公开(公告)号：US07091071B2
公开(公告)日：2006-08-15
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
发明人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

64. 发明申请

US20060170016A1 Asymmetric spacers and asymmetric source/drain extension layers 有权
标题翻译：非对称隔离层和不对称源极/漏极延伸层
公开(公告)号：US20060170016A1
公开(公告)日：2006-08-03
申请号：US11047946
申请日：2005-02-01
申请人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66659 , H01L29/7843
摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
摘要翻译：提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层，或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。

65. 发明申请

US20060148196A1 SEMICONDUCTOR FABRICATION PROCESS INCLUDING RECESSED SOURCE/DRAIN REGIONS IN AN SOI WAFER 有权
标题翻译：半导体制造工艺，包括SOI WAFER中的残留源/漏区
公开(公告)号：US20060148196A1
公开(公告)日：2006-07-06
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian Goolsby , Bich-Yen Nguyen , Thien Nguyen , Tab Stephens
发明人： Voon-Yew Thean , Brian Goolsby , Bich-Yen Nguyen , Thien Nguyen , Tab Stephens
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

66. 发明授权

US07067868B2 Double gate device having a heterojunction source/drain and strained channel 有权
公开(公告)号：US07067868B2
公开(公告)日：2006-06-27
申请号：US10952676
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

67. 发明授权

US07037795B1 Low RC product transistors in SOI semiconductor process 有权
标题翻译： SOI半导体工艺中的低RC产品晶体管
公开(公告)号：US07037795B1
公开(公告)日：2006-05-02
申请号：US10965964
申请日：2004-10-15
申请人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译：半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。源极/漏极结构形成在沟槽内。源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

68. 发明授权

US07018901B1 Method for forming a semiconductor device having a strained channel and a heterojunction source/drain 失效
标题翻译：用于形成具有应变通道和异质结源极/漏极的半导体器件的方法
公开(公告)号：US07018901B1
公开(公告)日：2006-03-28
申请号：US10954121
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam G. Sadaka , Ted R. White , Alexander L. Barr , Venkat R. Kolagunta , Bich-Yen Nguyen , Victor H. Vartanian , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

69. 发明授权

US08842945B2 Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates 有权
标题翻译：形成三维集成半导体系统的方法，包括光敏元件和绝缘体上半导体衬底
公开(公告)号：US08842945B2
公开(公告)日：2014-09-23
申请号：US13206299
申请日：2011-08-09
申请人： Bich-Yen Nguyen , Mariam Sadaka
发明人： Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： G02B6/12 , H01L25/16 , H01L27/06 , H01L31/103
CPC分类号： H01L25/167 , G02B6/12002 , G02B6/12004 , H01L27/0688 , H01L27/1203 , H01L31/103 , H01L33/34 , H01L2924/0002 , H01L2924/00
摘要： Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.
摘要翻译：三维集成的半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。光学互连可操作地耦合到光活性器件。半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。

70. 发明授权

US08617925B2 Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods 有权
标题翻译：在使用可恢复基板的3D积分处理中形成键合半导体结构的方法以及通过这些方法形成的结合的半导体结构
公开(公告)号：US08617925B2
公开(公告)日：2013-12-31
申请号：US13206280
申请日：2011-08-09
申请人： Mariam Sadaka , Bich-Yen Nguyen
发明人： Mariam Sadaka , Bich-Yen Nguyen
IPC分类号： H01L23/538 , H01L21/58 , H01L21/768
CPC分类号： H01L21/486 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L24/06 , H01L24/08 , H01L24/80 , H01L24/97 , H01L25/0652 , H01L25/50 , H01L2221/68345 , H01L2224/05009 , H01L2224/08146 , H01L2224/08235 , H01L2224/80099 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/97 , H01L2225/06541 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15311 , H01L2924/1816 , H01L2224/80 , H01L2224/03 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
摘要翻译：形成键合的半导体结构的方法包括通过晶片互连通过第一衬底结构的材料层形成，在材料层上结合一个或多个半导体结构，以及将半导体结构与贯穿晶片互连电连接。第二衬底结构可以在与第一衬底结构相对的一侧上结合在经处理的半导体结构上。然后可以去除第一衬底结构的一部分，留下其中附着有经处理的半导体结构的贯穿晶片互连的材料层。然后至少一个贯穿晶片互连可以电耦合到另一结构的导电特征，之后可以去除第二衬底结构。使用这种方法形成结合的半导体结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式